mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
136 lines
5.4 KiB
LLVM
136 lines
5.4 KiB
LLVM
; RUN: llc -march=arm64 -arm64-neon-syntax=apple -o - %s | FileCheck %s
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declare <16 x i8> @llvm.arm64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
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declare <16 x i8> @llvm.arm64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
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declare <16 x i8> @llvm.arm64.crypto.aesmc(<16 x i8> %data)
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declare <16 x i8> @llvm.arm64.crypto.aesimc(<16 x i8> %data)
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define <16 x i8> @test_aese(<16 x i8> %data, <16 x i8> %key) {
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; CHECK-LABEL: test_aese:
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; CHECK: aese.16b v0, v1
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%res = call <16 x i8> @llvm.arm64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
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ret <16 x i8> %res
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}
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define <16 x i8> @test_aesd(<16 x i8> %data, <16 x i8> %key) {
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; CHECK-LABEL: test_aesd:
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; CHECK: aesd.16b v0, v1
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%res = call <16 x i8> @llvm.arm64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
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ret <16 x i8> %res
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}
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define <16 x i8> @test_aesmc(<16 x i8> %data) {
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; CHECK-LABEL: test_aesmc:
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; CHECK: aesmc.16b v0, v0
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%res = call <16 x i8> @llvm.arm64.crypto.aesmc(<16 x i8> %data)
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ret <16 x i8> %res
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}
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define <16 x i8> @test_aesimc(<16 x i8> %data) {
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; CHECK-LABEL: test_aesimc:
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; CHECK: aesimc.16b v0, v0
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%res = call <16 x i8> @llvm.arm64.crypto.aesimc(<16 x i8> %data)
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ret <16 x i8> %res
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}
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declare <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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declare <4 x i32> @llvm.arm64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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declare <4 x i32> @llvm.arm64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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declare i32 @llvm.arm64.crypto.sha1h(i32 %hash_e)
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declare <4 x i32> @llvm.arm64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
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declare <4 x i32> @llvm.arm64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
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define <4 x i32> @test_sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
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; CHECK-LABEL: test_sha1c:
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; CHECK: fmov [[HASH_E:s[0-9]+]], w0
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; CHECK: sha1c.4s q0, [[HASH_E]], v1
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%res = call <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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ret <4 x i32> %res
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}
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; <rdar://problem/14742333> Incomplete removal of unnecessary FMOV instructions in intrinsic SHA1
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define <4 x i32> @test_sha1c_in_a_row(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
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; CHECK-LABEL: test_sha1c_in_a_row:
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; CHECK: fmov [[HASH_E:s[0-9]+]], w0
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; CHECK: sha1c.4s q[[SHA1RES:[0-9]+]], [[HASH_E]], v1
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; CHECK-NOT: fmov
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; CHECK: sha1c.4s q0, s[[SHA1RES]], v1
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%res = call <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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%extract = extractelement <4 x i32> %res, i32 0
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%res2 = call <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %extract, <4 x i32> %wk)
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ret <4 x i32> %res2
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}
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define <4 x i32> @test_sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
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; CHECK-LABEL: test_sha1p:
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; CHECK: fmov [[HASH_E:s[0-9]+]], w0
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; CHECK: sha1p.4s q0, [[HASH_E]], v1
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%res = call <4 x i32> @llvm.arm64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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ret <4 x i32> %res
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}
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define <4 x i32> @test_sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
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; CHECK-LABEL: test_sha1m:
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; CHECK: fmov [[HASH_E:s[0-9]+]], w0
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; CHECK: sha1m.4s q0, [[HASH_E]], v1
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%res = call <4 x i32> @llvm.arm64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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ret <4 x i32> %res
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}
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define i32 @test_sha1h(i32 %hash_e) {
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; CHECK-LABEL: test_sha1h:
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; CHECK: fmov [[HASH_E:s[0-9]+]], w0
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; CHECK: sha1h [[RES:s[0-9]+]], [[HASH_E]]
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; CHECK: fmov w0, [[RES]]
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%res = call i32 @llvm.arm64.crypto.sha1h(i32 %hash_e)
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ret i32 %res
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}
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define <4 x i32> @test_sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11) {
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; CHECK-LABEL: test_sha1su0:
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; CHECK: sha1su0.4s v0, v1, v2
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%res = call <4 x i32> @llvm.arm64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
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ret <4 x i32> %res
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}
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define <4 x i32> @test_sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15) {
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; CHECK-LABEL: test_sha1su1:
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; CHECK: sha1su1.4s v0, v1
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%res = call <4 x i32> @llvm.arm64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.arm64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
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declare <4 x i32> @llvm.arm64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
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declare <4 x i32> @llvm.arm64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
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declare <4 x i32> @llvm.arm64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
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define <4 x i32> @test_sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
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; CHECK-LABEL: test_sha256h:
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; CHECK: sha256h.4s q0, q1, v2
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%res = call <4 x i32> @llvm.arm64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
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ret <4 x i32> %res
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}
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define <4 x i32> @test_sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
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; CHECK-LABEL: test_sha256h2:
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; CHECK: sha256h2.4s q0, q1, v2
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%res = call <4 x i32> @llvm.arm64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
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ret <4 x i32> %res
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}
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define <4 x i32> @test_sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) {
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; CHECK-LABEL: test_sha256su0:
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; CHECK: sha256su0.4s v0, v1
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%res = call <4 x i32> @llvm.arm64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
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ret <4 x i32> %res
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}
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define <4 x i32> @test_sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
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; CHECK-LABEL: test_sha256su1:
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; CHECK: sha256su1.4s v0, v1, v2
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%res = call <4 x i32> @llvm.arm64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
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ret <4 x i32> %res
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}
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