mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153161 91177308-0d34-0410-b5e6-96231b3b80d8
614 lines
21 KiB
C++
614 lines
21 KiB
C++
//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// MachineScheduler schedules machine instructions after phi elimination. It
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// preserves LiveIntervals so it can be invoked before register allocation.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "misched"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/PriorityQueue.h"
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#include <queue>
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using namespace llvm;
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static cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
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cl::desc("Force top-down list scheduling"));
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static cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
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cl::desc("Force bottom-up list scheduling"));
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#ifndef NDEBUG
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static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
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cl::desc("Pop up a window to show MISched dags after they are processed"));
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static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
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cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
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#else
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static bool ViewMISchedDAGs = false;
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#endif // NDEBUG
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//===----------------------------------------------------------------------===//
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// Machine Instruction Scheduling Pass and Registry
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//===----------------------------------------------------------------------===//
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namespace {
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/// MachineScheduler runs after coalescing and before register allocation.
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class MachineScheduler : public MachineSchedContext,
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public MachineFunctionPass {
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public:
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MachineScheduler();
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory() {}
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virtual bool runOnMachineFunction(MachineFunction&);
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virtual void print(raw_ostream &O, const Module* = 0) const;
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static char ID; // Class identification, replacement for typeinfo
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};
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} // namespace
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char MachineScheduler::ID = 0;
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char &llvm::MachineSchedulerID = MachineScheduler::ID;
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INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
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"Machine Instruction Scheduler", false, false)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(MachineScheduler, "misched",
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"Machine Instruction Scheduler", false, false)
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MachineScheduler::MachineScheduler()
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: MachineFunctionPass(ID) {
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initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
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}
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void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequiredID(MachineDominatorsID);
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AU.addRequired<MachineLoopInfo>();
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AU.addRequired<AliasAnalysis>();
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AU.addRequired<TargetPassConfig>();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachinePassRegistry MachineSchedRegistry::Registry;
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/// A dummy default scheduler factory indicates whether the scheduler
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/// is overridden on the command line.
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static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
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return 0;
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}
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/// MachineSchedOpt allows command line selection of the scheduler.
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static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
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RegisterPassParser<MachineSchedRegistry> >
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MachineSchedOpt("misched",
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cl::init(&useDefaultMachineSched), cl::Hidden,
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cl::desc("Machine instruction scheduler to use"));
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static MachineSchedRegistry
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DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
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useDefaultMachineSched);
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/// Forward declare the standard machine scheduler. This will be used as the
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/// default scheduler if the target does not set a default.
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static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C);
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/// Top-level MachineScheduler pass driver.
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///
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/// Visit blocks in function order. Divide each block into scheduling regions
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/// and visit them bottom-up. Visiting regions bottom-up is not required, but is
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/// consistent with the DAG builder, which traverses the interior of the
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/// scheduling regions bottom-up.
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///
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/// This design avoids exposing scheduling boundaries to the DAG builder,
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/// simplifying the DAG builder's support for "special" target instructions.
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/// At the same time the design allows target schedulers to operate across
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/// scheduling boundaries, for example to bundle the boudary instructions
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/// without reordering them. This creates complexity, because the target
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/// scheduler must update the RegionBegin and RegionEnd positions cached by
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/// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
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/// design would be to split blocks at scheduling boundaries, but LLVM has a
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/// general bias against block splitting purely for implementation simplicity.
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bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
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// Initialize the context of the pass.
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MF = &mf;
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MLI = &getAnalysis<MachineLoopInfo>();
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MDT = &getAnalysis<MachineDominatorTree>();
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PassConfig = &getAnalysis<TargetPassConfig>();
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AA = &getAnalysis<AliasAnalysis>();
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LIS = &getAnalysis<LiveIntervals>();
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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// Select the scheduler, or set the default.
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MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
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if (Ctor == useDefaultMachineSched) {
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// Get the default scheduler set by the target.
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Ctor = MachineSchedRegistry::getDefault();
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if (!Ctor) {
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Ctor = createConvergingSched;
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MachineSchedRegistry::setDefault(Ctor);
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}
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}
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// Instantiate the selected scheduler.
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OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
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// Visit all machine basic blocks.
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for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
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MBB != MBBEnd; ++MBB) {
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Scheduler->startBlock(MBB);
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// Break the block into scheduling regions [I, RegionEnd), and schedule each
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// region as soon as it is discovered. RegionEnd points the the scheduling
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// boundary at the bottom of the region. The DAG does not include RegionEnd,
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// but the region does (i.e. the next RegionEnd is above the previous
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// RegionBegin). If the current block has no terminator then RegionEnd ==
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// MBB->end() for the bottom region.
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//
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// The Scheduler may insert instructions during either schedule() or
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// exitRegion(), even for empty regions. So the local iterators 'I' and
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// 'RegionEnd' are invalid across these calls.
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unsigned RemainingCount = MBB->size();
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for(MachineBasicBlock::iterator RegionEnd = MBB->end();
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RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
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// Avoid decrementing RegionEnd for blocks with no terminator.
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if (RegionEnd != MBB->end()
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|| TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
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--RegionEnd;
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// Count the boundary instruction.
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--RemainingCount;
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}
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// The next region starts above the previous region. Look backward in the
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// instruction stream until we find the nearest boundary.
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MachineBasicBlock::iterator I = RegionEnd;
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for(;I != MBB->begin(); --I, --RemainingCount) {
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if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
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break;
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}
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// Notify the scheduler of the region, even if we may skip scheduling
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// it. Perhaps it still needs to be bundled.
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Scheduler->enterRegion(MBB, I, RegionEnd, RemainingCount);
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// Skip empty scheduling regions (0 or 1 schedulable instructions).
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if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
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// Close the current region. Bundle the terminator if needed.
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// This invalidates 'RegionEnd' and 'I'.
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Scheduler->exitRegion();
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continue;
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}
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DEBUG(dbgs() << "MachineScheduling " << MF->getFunction()->getName()
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<< ":BB#" << MBB->getNumber() << "\n From: " << *I << " To: ";
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if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
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else dbgs() << "End";
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dbgs() << " Remaining: " << RemainingCount << "\n");
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// Schedule a region: possibly reorder instructions.
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// This invalidates 'RegionEnd' and 'I'.
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Scheduler->schedule();
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// Close the current region.
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Scheduler->exitRegion();
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// Scheduling has invalidated the current iterator 'I'. Ask the
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// scheduler for the top of it's scheduled region.
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RegionEnd = Scheduler->begin();
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}
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assert(RemainingCount == 0 && "Instruction count mismatch!");
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Scheduler->finishBlock();
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}
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DEBUG(LIS->print(dbgs()));
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return true;
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}
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void MachineScheduler::print(raw_ostream &O, const Module* m) const {
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// unimplemented
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}
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//===----------------------------------------------------------------------===//
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// MachineSchedStrategy - Interface to a machine scheduling algorithm.
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//===----------------------------------------------------------------------===//
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namespace {
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class ScheduleDAGMI;
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/// MachineSchedStrategy - Interface used by ScheduleDAGMI to drive the selected
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/// scheduling algorithm.
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///
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/// If this works well and targets wish to reuse ScheduleDAGMI, we may expose it
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/// in ScheduleDAGInstrs.h
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class MachineSchedStrategy {
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public:
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virtual ~MachineSchedStrategy() {}
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/// Initialize the strategy after building the DAG for a new region.
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virtual void initialize(ScheduleDAGMI *DAG) = 0;
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/// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
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/// schedule the node at the top of the unscheduled region. Otherwise it will
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/// be scheduled at the bottom.
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virtual SUnit *pickNode(bool &IsTopNode) = 0;
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/// When all predecessor dependencies have been resolved, free this node for
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/// top-down scheduling.
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virtual void releaseTopNode(SUnit *SU) = 0;
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/// When all successor dependencies have been resolved, free this node for
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/// bottom-up scheduling.
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virtual void releaseBottomNode(SUnit *SU) = 0;
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};
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} // namespace
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//===----------------------------------------------------------------------===//
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// ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals
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// preservation.
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//===----------------------------------------------------------------------===//
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namespace {
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/// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
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/// machine instructions while updating LiveIntervals.
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class ScheduleDAGMI : public ScheduleDAGInstrs {
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AliasAnalysis *AA;
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MachineSchedStrategy *SchedImpl;
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/// The top of the unscheduled zone.
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MachineBasicBlock::iterator CurrentTop;
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/// The bottom of the unscheduled zone.
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MachineBasicBlock::iterator CurrentBottom;
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/// The number of instructions scheduled so far. Used to cut off the
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/// scheduler at the point determined by misched-cutoff.
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unsigned NumInstrsScheduled;
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public:
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ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
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ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
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AA(C->AA), SchedImpl(S), CurrentTop(), CurrentBottom(),
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NumInstrsScheduled(0) {}
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~ScheduleDAGMI() {
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delete SchedImpl;
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}
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MachineBasicBlock::iterator top() const { return CurrentTop; }
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MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
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/// Implement ScheduleDAGInstrs interface.
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void schedule();
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protected:
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void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
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bool checkSchedLimit();
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void releaseSucc(SUnit *SU, SDep *SuccEdge);
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void releaseSuccessors(SUnit *SU);
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void releasePred(SUnit *SU, SDep *PredEdge);
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void releasePredecessors(SUnit *SU);
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};
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} // namespace
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
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/// NumPredsLeft reaches zero, release the successor node.
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void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
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SUnit *SuccSU = SuccEdge->getSUnit();
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#ifndef NDEBUG
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if (SuccSU->NumPredsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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SuccSU->dump(this);
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dbgs() << " has been released too many times!\n";
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llvm_unreachable(0);
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}
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#endif
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--SuccSU->NumPredsLeft;
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if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
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SchedImpl->releaseTopNode(SuccSU);
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}
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/// releaseSuccessors - Call releaseSucc on each of SU's successors.
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void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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releaseSucc(SU, &*I);
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}
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}
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
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/// NumSuccsLeft reaches zero, release the predecessor node.
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void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
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SUnit *PredSU = PredEdge->getSUnit();
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#ifndef NDEBUG
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if (PredSU->NumSuccsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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PredSU->dump(this);
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dbgs() << " has been released too many times!\n";
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llvm_unreachable(0);
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}
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#endif
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--PredSU->NumSuccsLeft;
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if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
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SchedImpl->releaseBottomNode(PredSU);
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}
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/// releasePredecessors - Call releasePred on each of SU's predecessors.
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void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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releasePred(SU, &*I);
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}
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}
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void ScheduleDAGMI::moveInstruction(MachineInstr *MI,
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MachineBasicBlock::iterator InsertPos) {
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// Fix RegionBegin if the first instruction moves down.
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if (&*RegionBegin == MI)
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RegionBegin = llvm::next(RegionBegin);
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BB->splice(InsertPos, BB, MI);
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LIS->handleMove(MI);
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// Fix RegionBegin if another instruction moves above the first instruction.
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if (RegionBegin == InsertPos)
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RegionBegin = MI;
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}
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bool ScheduleDAGMI::checkSchedLimit() {
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#ifndef NDEBUG
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if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
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CurrentTop = CurrentBottom;
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return false;
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}
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++NumInstrsScheduled;
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#endif
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return true;
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}
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/// schedule - Called back from MachineScheduler::runOnMachineFunction
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/// after setting up the current scheduling region.
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void ScheduleDAGMI::schedule() {
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buildSchedGraph(AA);
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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if (ViewMISchedDAGs) viewGraph();
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SchedImpl->initialize(this);
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// Release edges from the special Entry node or to the special Exit node.
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releaseSuccessors(&EntrySU);
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releasePredecessors(&ExitSU);
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// Release all DAG roots for scheduling.
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for (std::vector<SUnit>::iterator I = SUnits.begin(), E = SUnits.end();
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I != E; ++I) {
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// A SUnit is ready to top schedule if it has no predecessors.
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if (I->Preds.empty())
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SchedImpl->releaseTopNode(&(*I));
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// A SUnit is ready to bottom schedule if it has no successors.
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if (I->Succs.empty())
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SchedImpl->releaseBottomNode(&(*I));
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}
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CurrentTop = RegionBegin;
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CurrentBottom = RegionEnd;
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bool IsTopNode = false;
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while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
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DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom")
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<< " Scheduling Instruction:\n"; SU->dump(this));
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if (!checkSchedLimit())
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break;
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// Move the instruction to its new location in the instruction stream.
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MachineInstr *MI = SU->getInstr();
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if (IsTopNode) {
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assert(SU->isTopReady() && "node still has unscheduled dependencies");
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if (&*CurrentTop == MI)
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++CurrentTop;
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else
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moveInstruction(MI, CurrentTop);
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// Release dependent instructions for scheduling.
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releaseSuccessors(SU);
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}
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else {
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assert(SU->isBottomReady() && "node still has unscheduled dependencies");
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if (&*llvm::prior(CurrentBottom) == MI)
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--CurrentBottom;
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else {
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if (&*CurrentTop == MI)
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CurrentTop = llvm::next(CurrentTop);
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moveInstruction(MI, CurrentBottom);
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CurrentBottom = MI;
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}
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// Release dependent instructions for scheduling.
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releasePredecessors(SU);
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}
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SU->isScheduled = true;
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}
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assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
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}
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//===----------------------------------------------------------------------===//
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// ConvergingScheduler - Implementation of the standard MachineSchedStrategy.
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//===----------------------------------------------------------------------===//
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namespace {
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/// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance
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/// the schedule.
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class ConvergingScheduler : public MachineSchedStrategy {
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ScheduleDAGMI *DAG;
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unsigned NumTopReady;
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unsigned NumBottomReady;
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public:
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virtual void initialize(ScheduleDAGMI *dag) {
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DAG = dag;
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assert((!ForceTopDown || !ForceBottomUp) &&
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"-misched-topdown incompatible with -misched-bottomup");
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}
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virtual SUnit *pickNode(bool &IsTopNode) {
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if (DAG->top() == DAG->bottom())
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return NULL;
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// As an initial placeholder heuristic, schedule in the direction that has
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// the fewest choices.
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SUnit *SU;
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if (ForceTopDown || (!ForceBottomUp && NumTopReady <= NumBottomReady)) {
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SU = DAG->getSUnit(DAG->top());
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IsTopNode = true;
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}
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else {
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SU = DAG->getSUnit(llvm::prior(DAG->bottom()));
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IsTopNode = false;
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}
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if (SU->isTopReady()) {
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assert(NumTopReady > 0 && "bad ready count");
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--NumTopReady;
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}
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|
if (SU->isBottomReady()) {
|
|
assert(NumBottomReady > 0 && "bad ready count");
|
|
--NumBottomReady;
|
|
}
|
|
return SU;
|
|
}
|
|
|
|
virtual void releaseTopNode(SUnit *SU) {
|
|
++NumTopReady;
|
|
}
|
|
virtual void releaseBottomNode(SUnit *SU) {
|
|
++NumBottomReady;
|
|
}
|
|
};
|
|
} // namespace
|
|
|
|
/// Create the standard converging machine scheduler. This will be used as the
|
|
/// default scheduler if the target does not set a default.
|
|
static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
|
|
assert((!ForceTopDown || !ForceBottomUp) &&
|
|
"-misched-topdown incompatible with -misched-bottomup");
|
|
return new ScheduleDAGMI(C, new ConvergingScheduler());
|
|
}
|
|
static MachineSchedRegistry
|
|
ConvergingSchedRegistry("converge", "Standard converging scheduler.",
|
|
createConvergingSched);
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Machine Instruction Shuffler for Correctness Testing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef NDEBUG
|
|
namespace {
|
|
/// Apply a less-than relation on the node order, which corresponds to the
|
|
/// instruction order prior to scheduling. IsReverse implements greater-than.
|
|
template<bool IsReverse>
|
|
struct SUnitOrder {
|
|
bool operator()(SUnit *A, SUnit *B) const {
|
|
if (IsReverse)
|
|
return A->NodeNum > B->NodeNum;
|
|
else
|
|
return A->NodeNum < B->NodeNum;
|
|
}
|
|
};
|
|
|
|
/// Reorder instructions as much as possible.
|
|
class InstructionShuffler : public MachineSchedStrategy {
|
|
bool IsAlternating;
|
|
bool IsTopDown;
|
|
|
|
// Using a less-than relation (SUnitOrder<false>) for the TopQ priority
|
|
// gives nodes with a higher number higher priority causing the latest
|
|
// instructions to be scheduled first.
|
|
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
|
|
TopQ;
|
|
// When scheduling bottom-up, use greater-than as the queue priority.
|
|
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
|
|
BottomQ;
|
|
public:
|
|
InstructionShuffler(bool alternate, bool topdown)
|
|
: IsAlternating(alternate), IsTopDown(topdown) {}
|
|
|
|
virtual void initialize(ScheduleDAGMI *) {
|
|
TopQ.clear();
|
|
BottomQ.clear();
|
|
}
|
|
|
|
/// Implement MachineSchedStrategy interface.
|
|
/// -----------------------------------------
|
|
|
|
virtual SUnit *pickNode(bool &IsTopNode) {
|
|
SUnit *SU;
|
|
if (IsTopDown) {
|
|
do {
|
|
if (TopQ.empty()) return NULL;
|
|
SU = TopQ.top();
|
|
TopQ.pop();
|
|
} while (SU->isScheduled);
|
|
IsTopNode = true;
|
|
}
|
|
else {
|
|
do {
|
|
if (BottomQ.empty()) return NULL;
|
|
SU = BottomQ.top();
|
|
BottomQ.pop();
|
|
} while (SU->isScheduled);
|
|
IsTopNode = false;
|
|
}
|
|
if (IsAlternating)
|
|
IsTopDown = !IsTopDown;
|
|
return SU;
|
|
}
|
|
|
|
virtual void releaseTopNode(SUnit *SU) {
|
|
TopQ.push(SU);
|
|
}
|
|
virtual void releaseBottomNode(SUnit *SU) {
|
|
BottomQ.push(SU);
|
|
}
|
|
};
|
|
} // namespace
|
|
|
|
static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
|
|
bool Alternate = !ForceTopDown && !ForceBottomUp;
|
|
bool TopDown = !ForceBottomUp;
|
|
assert((TopDown || !ForceTopDown) &&
|
|
"-misched-topdown incompatible with -misched-bottomup");
|
|
return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown));
|
|
}
|
|
static MachineSchedRegistry ShufflerRegistry(
|
|
"shuffle", "Shuffle machine instructions alternating directions",
|
|
createInstructionShuffler);
|
|
#endif // !NDEBUG
|