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https://github.com/c64scene-ar/llvm-6502.git
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547ba56bd0
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. PR22883 was caused the matching operands copying the whole of the operand flags for the matched operand. This included the constraint id which needed to be replaced with the operand number. This has been fixed with a conversion function. Following on from this, matching operands also used the operand number as the constraint id. This has been fixed by looking up the matched operand and taking it from there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232165 91177308-0d34-0410-b5e6-96231b3b80d8
134 lines
5.3 KiB
C++
134 lines
5.3 KiB
C++
//===---- MipsISelDAGToDAG.h - A Dag to Dag Inst Selector for Mips --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MIPS target.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H
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#define LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace llvm {
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class MipsDAGToDAGISel : public SelectionDAGISel {
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public:
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explicit MipsDAGToDAGISel(MipsTargetMachine &TM)
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: SelectionDAGISel(TM), Subtarget(nullptr) {}
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// Pass Name
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const char *getPassName() const override {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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protected:
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SDNode *getGlobalBaseReg();
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/// Keep a pointer to the MipsSubtarget around so that we can make the right
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/// decision when generating code for different targets.
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const MipsSubtarget *Subtarget;
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private:
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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// Complex Pattern.
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/// (reg + imm).
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virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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// Complex Pattern.
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/// (reg + reg).
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virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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/// Fall back on this function if all else fails.
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virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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/// Match integer address pattern.
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virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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/// Match addr+simm10 and addr
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virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
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SDValue &Offset, SDValue &Alias);
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/// \brief Select constant vector splats.
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virtual bool selectVSplat(SDNode *N, APInt &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm1.
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virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm2.
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virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm3.
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virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm4.
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virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm5.
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virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm6.
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virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm8.
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virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a simm5.
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virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value is a power of 2.
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virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value is the inverse of a
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/// power of 2.
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virtual bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value is a run of set bits
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/// ending at the most significant bit
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virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value is a run of set bits
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/// starting at bit zero.
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virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
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SDNode *Select(SDNode *N) override;
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virtual std::pair<bool, SDNode*> selectNode(SDNode *Node) = 0;
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// getImm - Return a target constant with the specified value.
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inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
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return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
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}
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virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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};
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}
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#endif
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