mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 19:55:11 +00:00
fef8e383eb
If we know that a particular 64-bit constant has all high bits zero, then we can rely on the fact that 32-bit ARM64 instructions automatically zero out the high bits of an x-register. This gives the expansion logic less constraints to satisfy and so sometimes allows it to pick better sequences. Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a 32-bit MOVN to be used in @test8 soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206379 91177308-0d34-0410-b5e6-96231b3b80d8
223 lines
5.4 KiB
LLVM
223 lines
5.4 KiB
LLVM
; RUN: llc -O3 < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
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target triple = "arm64-unknown-unknown"
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; CHECK: foo1
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; CHECK: csinc w{{[0-9]+}}, w[[REG:[0-9]+]],
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; CHECK: w[[REG]], eq
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define i32 @foo1(i32 %b, i32 %c) nounwind readnone ssp {
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entry:
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%not.tobool = icmp ne i32 %c, 0
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%add = zext i1 %not.tobool to i32
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%b.add = add i32 %c, %b
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%add1 = add i32 %b.add, %add
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ret i32 %add1
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}
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; CHECK: foo2
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; CHECK: csneg w{{[0-9]+}}, w[[REG:[0-9]+]],
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; CHECK: w[[REG]], eq
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define i32 @foo2(i32 %b, i32 %c) nounwind readnone ssp {
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entry:
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%mul = sub i32 0, %b
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%tobool = icmp eq i32 %c, 0
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%b.mul = select i1 %tobool, i32 %b, i32 %mul
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%add = add nsw i32 %b.mul, %c
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ret i32 %add
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}
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; CHECK: foo3
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; CHECK: csinv w{{[0-9]+}}, w[[REG:[0-9]+]],
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; CHECK: w[[REG]], eq
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define i32 @foo3(i32 %b, i32 %c) nounwind readnone ssp {
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entry:
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%not.tobool = icmp ne i32 %c, 0
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%xor = sext i1 %not.tobool to i32
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%b.xor = xor i32 %xor, %b
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%add = add nsw i32 %b.xor, %c
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ret i32 %add
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}
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; rdar://11632325
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define i32@foo4(i32 %a) nounwind ssp {
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; CHECK: foo4
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; CHECK: csneg
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; CHECK-NEXT: ret
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%cmp = icmp sgt i32 %a, -1
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%neg = sub nsw i32 0, %a
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%cond = select i1 %cmp, i32 %a, i32 %neg
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ret i32 %cond
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}
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define i32@foo5(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: foo5
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; CHECK: subs
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; CHECK-NEXT: csneg
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; CHECK-NEXT: ret
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%sub = sub nsw i32 %a, %b
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%cmp = icmp sgt i32 %sub, -1
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%sub3 = sub nsw i32 0, %sub
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%cond = select i1 %cmp, i32 %sub, i32 %sub3
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ret i32 %cond
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}
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; make sure we can handle branch instruction in optimizeCompare.
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define i32@foo6(i32 %a, i32 %b) nounwind ssp {
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; CHECK: foo6
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; CHECK: b
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%sub = sub nsw i32 %a, %b
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%cmp = icmp sgt i32 %sub, 0
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br i1 %cmp, label %l.if, label %l.else
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l.if:
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ret i32 1
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l.else:
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ret i32 %sub
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}
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; If CPSR is used multiple times and V flag is used, we don't remove cmp.
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define i32 @foo7(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: foo7:
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; CHECK: sub
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; CHECK-next: adds
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; CHECK-next: csneg
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; CHECK-next: b
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%sub = sub nsw i32 %a, %b
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%cmp = icmp sgt i32 %sub, -1
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%sub3 = sub nsw i32 0, %sub
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%cond = select i1 %cmp, i32 %sub, i32 %sub3
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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%cmp2 = icmp slt i32 %sub, -1
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%sel = select i1 %cmp2, i32 %cond, i32 %a
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ret i32 %sel
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if.else:
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ret i32 %cond
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}
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define i32 @foo8(i32 %v, i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: foo8:
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; CHECK: cmp w0, #0
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; CHECK: csinv w0, w1, w2, ne
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%tobool = icmp eq i32 %v, 0
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%neg = xor i32 -1, %b
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%cond = select i1 %tobool, i32 %neg, i32 %a
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ret i32 %cond
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}
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define i32 @foo9(i32 %v) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo9:
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; CHECK: cmp w0, #0
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; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
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; CHECK: csinv w0, w[[REG]], w[[REG]], ne
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%tobool = icmp ne i32 %v, 0
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%cond = select i1 %tobool, i32 4, i32 -5
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ret i32 %cond
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}
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define i64 @foo10(i64 %v) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo10:
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; CHECK: cmp x0, #0
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; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
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; CHECK: csinv x0, x[[REG]], x[[REG]], ne
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%tobool = icmp ne i64 %v, 0
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%cond = select i1 %tobool, i64 4, i64 -5
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ret i64 %cond
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}
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define i32 @foo11(i32 %v) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo11:
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; CHECK: cmp w0, #0
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; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
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; CHECK: csneg w0, w[[REG]], w[[REG]], ne
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%tobool = icmp ne i32 %v, 0
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%cond = select i1 %tobool, i32 4, i32 -4
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ret i32 %cond
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}
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define i64 @foo12(i64 %v) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo12:
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; CHECK: cmp x0, #0
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; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
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; CHECK: csneg x0, x[[REG]], x[[REG]], ne
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%tobool = icmp ne i64 %v, 0
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%cond = select i1 %tobool, i64 4, i64 -4
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ret i64 %cond
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}
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define i32 @foo13(i32 %v, i32 %a, i32 %b) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo13:
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; CHECK: cmp w0, #0
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; CHECK: csneg w0, w1, w2, ne
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%tobool = icmp eq i32 %v, 0
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%sub = sub i32 0, %b
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%cond = select i1 %tobool, i32 %sub, i32 %a
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ret i32 %cond
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}
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define i64 @foo14(i64 %v, i64 %a, i64 %b) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo14:
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; CHECK: cmp x0, #0
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; CHECK: csneg x0, x1, x2, ne
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%tobool = icmp eq i64 %v, 0
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%sub = sub i64 0, %b
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%cond = select i1 %tobool, i64 %sub, i64 %a
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ret i64 %cond
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}
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define i32 @foo15(i32 %a, i32 %b) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo15:
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; CHECK: cmp w0, w1
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; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
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; CHECK: csinc w0, w[[REG]], w[[REG]], le
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%cmp = icmp sgt i32 %a, %b
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%. = select i1 %cmp, i32 2, i32 1
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ret i32 %.
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}
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define i32 @foo16(i32 %a, i32 %b) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo16:
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; CHECK: cmp w0, w1
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; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
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; CHECK: csinc w0, w[[REG]], w[[REG]], gt
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%cmp = icmp sgt i32 %a, %b
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%. = select i1 %cmp, i32 1, i32 2
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ret i32 %.
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}
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define i64 @foo17(i64 %a, i64 %b) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo17:
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; CHECK: cmp x0, x1
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; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
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; CHECK: csinc x0, x[[REG]], x[[REG]], le
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%cmp = icmp sgt i64 %a, %b
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%. = select i1 %cmp, i64 2, i64 1
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ret i64 %.
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}
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define i64 @foo18(i64 %a, i64 %b) nounwind readnone optsize ssp {
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entry:
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; CHECK-LABEL: foo18:
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; CHECK: cmp x0, x1
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; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
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; CHECK: csinc x0, x[[REG]], x[[REG]], gt
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%cmp = icmp sgt i64 %a, %b
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%. = select i1 %cmp, i64 1, i64 2
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ret i64 %.
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}
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