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https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
511 lines
18 KiB
C++
511 lines
18 KiB
C++
//===-- AArch64BranchRelaxation.cpp - AArch64 branch relaxation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-branch-relax"
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static cl::opt<bool>
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BranchRelaxation("aarch64-branch-relax", cl::Hidden, cl::init(true),
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cl::desc("Relax out of range conditional branches"));
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static cl::opt<unsigned>
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TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
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cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"));
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static cl::opt<unsigned>
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CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
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cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"));
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static cl::opt<unsigned>
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BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
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cl::desc("Restrict range of Bcc instructions (DEBUG)"));
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STATISTIC(NumSplit, "Number of basic blocks split");
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STATISTIC(NumRelaxed, "Number of conditional branches relaxed");
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namespace {
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class AArch64BranchRelaxation : public MachineFunctionPass {
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/// BasicBlockInfo - Information about the offset and size of a single
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/// basic block.
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struct BasicBlockInfo {
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/// Offset - Distance from the beginning of the function to the beginning
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/// of this basic block.
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///
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/// The offset is always aligned as required by the basic block.
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unsigned Offset;
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/// Size - Size of the basic block in bytes. If the block contains
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/// inline assembly, this is a worst case estimate.
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///
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/// The size does not include any alignment padding whether from the
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/// beginning of the block, or from an aligned jump table at the end.
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unsigned Size;
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BasicBlockInfo() : Offset(0), Size(0) {}
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/// Compute the offset immediately following this block. If LogAlign is
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/// specified, return the offset the successor block will get if it has
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/// this alignment.
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unsigned postOffset(unsigned LogAlign = 0) const {
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unsigned PO = Offset + Size;
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unsigned Align = 1 << LogAlign;
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return (PO + Align - 1) / Align * Align;
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}
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};
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SmallVector<BasicBlockInfo, 16> BlockInfo;
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MachineFunction *MF;
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const AArch64InstrInfo *TII;
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bool relaxBranchInstructions();
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void scanFunction();
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MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
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void adjustBlockOffsets(MachineBasicBlock &MBB);
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bool isBlockInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
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bool fixupConditionalBranch(MachineInstr *MI);
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void computeBlockSize(const MachineBasicBlock &MBB);
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unsigned getInstrOffset(MachineInstr *MI) const;
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void dumpBBs();
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void verify();
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public:
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static char ID;
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AArch64BranchRelaxation() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "AArch64 branch relaxation pass";
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}
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};
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char AArch64BranchRelaxation::ID = 0;
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}
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/// verify - check BBOffsets, BBSizes, alignment of islands
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void AArch64BranchRelaxation::verify() {
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#ifndef NDEBUG
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unsigned PrevNum = MF->begin()->getNumber();
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for (MachineBasicBlock &MBB : *MF) {
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unsigned Align = MBB.getAlignment();
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unsigned Num = MBB.getNumber();
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assert(BlockInfo[Num].Offset % (1u << Align) == 0);
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assert(!Num || BlockInfo[PrevNum].postOffset() <= BlockInfo[Num].Offset);
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PrevNum = Num;
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}
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#endif
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}
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/// print block size and offset information - debugging
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void AArch64BranchRelaxation::dumpBBs() {
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for (auto &MBB : *MF) {
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const BasicBlockInfo &BBI = BlockInfo[MBB.getNumber()];
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dbgs() << format("BB#%u\toffset=%08x\t", MBB.getNumber(), BBI.Offset)
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<< format("size=%#x\n", BBI.Size);
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}
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}
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/// BBHasFallthrough - Return true if the specified basic block can fallthrough
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/// into the block immediately after it.
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static bool BBHasFallthrough(MachineBasicBlock *MBB) {
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// Get the next machine basic block in the function.
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MachineFunction::iterator MBBI = MBB;
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// Can't fall off end of function.
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MachineBasicBlock *NextBB = std::next(MBBI);
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if (NextBB == MBB->getParent()->end())
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return false;
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for (MachineBasicBlock *S : MBB->successors())
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if (S == NextBB)
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return true;
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return false;
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}
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/// scanFunction - Do the initial scan of the function, building up
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/// information about each block.
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void AArch64BranchRelaxation::scanFunction() {
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BlockInfo.clear();
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BlockInfo.resize(MF->getNumBlockIDs());
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// First thing, compute the size of all basic blocks, and see if the function
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// has any inline assembly in it. If so, we have to be conservative about
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// alignment assumptions, as we don't know for sure the size of any
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// instructions in the inline assembly.
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for (MachineBasicBlock &MBB : *MF)
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computeBlockSize(MBB);
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// Compute block offsets and known bits.
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adjustBlockOffsets(*MF->begin());
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}
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/// computeBlockSize - Compute the size for MBB.
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/// This function updates BlockInfo directly.
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void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) {
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unsigned Size = 0;
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for (const MachineInstr &MI : MBB)
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Size += TII->GetInstSizeInBytes(&MI);
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BlockInfo[MBB.getNumber()].Size = Size;
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}
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/// getInstrOffset - Return the current offset of the specified machine
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/// instruction from the start of the function. This offset changes as stuff is
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/// moved around inside the function.
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unsigned AArch64BranchRelaxation::getInstrOffset(MachineInstr *MI) const {
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MachineBasicBlock *MBB = MI->getParent();
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// The offset is composed of two things: the sum of the sizes of all MBB's
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// before this instruction's block, and the offset from the start of the block
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// it is in.
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unsigned Offset = BlockInfo[MBB->getNumber()].Offset;
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// Sum instructions before MI in MBB.
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for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
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assert(I != MBB->end() && "Didn't find MI in its own basic block?");
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Offset += TII->GetInstSizeInBytes(I);
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}
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return Offset;
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}
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void AArch64BranchRelaxation::adjustBlockOffsets(MachineBasicBlock &Start) {
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unsigned PrevNum = Start.getNumber();
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for (auto &MBB : make_range(MachineFunction::iterator(Start), MF->end())) {
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unsigned Num = MBB.getNumber();
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if (!Num) // block zero is never changed from offset zero.
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continue;
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// Get the offset and known bits at the end of the layout predecessor.
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// Include the alignment of the current block.
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unsigned LogAlign = MBB.getAlignment();
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BlockInfo[Num].Offset = BlockInfo[PrevNum].postOffset(LogAlign);
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PrevNum = Num;
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}
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}
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/// Split the basic block containing MI into two blocks, which are joined by
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/// an unconditional branch. Update data structures and renumber blocks to
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/// account for this change and returns the newly created block.
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/// NOTE: Successor list of the original BB is out of date after this function,
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/// and must be updated by the caller! Other transforms follow using this
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/// utility function, so no point updating now rather than waiting.
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MachineBasicBlock *
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AArch64BranchRelaxation::splitBlockBeforeInstr(MachineInstr *MI) {
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MachineBasicBlock *OrigBB = MI->getParent();
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// Create a new MBB for the code after the OrigBB.
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MachineBasicBlock *NewBB =
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MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
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MachineFunction::iterator MBBI = OrigBB;
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++MBBI;
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MF->insert(MBBI, NewBB);
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// Splice the instructions starting with MI over to NewBB.
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NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
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// Add an unconditional branch from OrigBB to NewBB.
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// Note the new unconditional branch is not being recorded.
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// There doesn't seem to be meaningful DebugInfo available; this doesn't
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// correspond to anything in the source.
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BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB);
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// Insert an entry into BlockInfo to align it properly with the block numbers.
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BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
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// Figure out how large the OrigBB is. As the first half of the original
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// block, it cannot contain a tablejump. The size includes
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// the new jump we added. (It should be possible to do this without
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// recounting everything, but it's very confusing, and this is rarely
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// executed.)
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computeBlockSize(*OrigBB);
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// Figure out how large the NewMBB is. As the second half of the original
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// block, it may contain a tablejump.
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computeBlockSize(*NewBB);
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// All BBOffsets following these blocks must be modified.
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adjustBlockOffsets(*OrigBB);
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++NumSplit;
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return NewBB;
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}
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/// isBlockInRange - Returns true if the distance between specific MI and
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/// specific BB can fit in MI's displacement field.
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bool AArch64BranchRelaxation::isBlockInRange(MachineInstr *MI,
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MachineBasicBlock *DestBB,
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unsigned Bits) {
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unsigned MaxOffs = ((1 << (Bits - 1)) - 1) << 2;
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unsigned BrOffset = getInstrOffset(MI);
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unsigned DestOffset = BlockInfo[DestBB->getNumber()].Offset;
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DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
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<< " from BB#" << MI->getParent()->getNumber()
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<< " max delta=" << MaxOffs << " from " << getInstrOffset(MI)
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<< " to " << DestOffset << " offset "
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<< int(DestOffset - BrOffset) << "\t" << *MI);
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// Branch before the Dest.
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if (BrOffset <= DestOffset)
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return (DestOffset - BrOffset <= MaxOffs);
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return (BrOffset - DestOffset <= MaxOffs);
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}
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static bool isConditionalBranch(unsigned Opc) {
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switch (Opc) {
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default:
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return false;
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case AArch64::TBZW:
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case AArch64::TBNZW:
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case AArch64::TBZX:
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case AArch64::TBNZX:
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case AArch64::CBZW:
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case AArch64::CBNZW:
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case AArch64::CBZX:
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case AArch64::CBNZX:
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case AArch64::Bcc:
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return true;
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}
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}
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static MachineBasicBlock *getDestBlock(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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default:
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assert(0 && "unexpected opcode!");
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case AArch64::TBZW:
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case AArch64::TBNZW:
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case AArch64::TBZX:
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case AArch64::TBNZX:
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return MI->getOperand(2).getMBB();
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case AArch64::CBZW:
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case AArch64::CBNZW:
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case AArch64::CBZX:
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case AArch64::CBNZX:
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case AArch64::Bcc:
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return MI->getOperand(1).getMBB();
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}
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}
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static unsigned getOppositeConditionOpcode(unsigned Opc) {
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switch (Opc) {
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default:
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assert(0 && "unexpected opcode!");
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case AArch64::TBNZW: return AArch64::TBZW;
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case AArch64::TBNZX: return AArch64::TBZX;
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case AArch64::TBZW: return AArch64::TBNZW;
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case AArch64::TBZX: return AArch64::TBNZX;
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case AArch64::CBNZW: return AArch64::CBZW;
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case AArch64::CBNZX: return AArch64::CBZX;
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case AArch64::CBZW: return AArch64::CBNZW;
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case AArch64::CBZX: return AArch64::CBNZX;
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case AArch64::Bcc: return AArch64::Bcc; // Condition is an operand for Bcc.
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}
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}
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static unsigned getBranchDisplacementBits(unsigned Opc) {
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switch (Opc) {
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default:
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assert(0 && "unexpected opcode!");
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case AArch64::TBNZW:
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case AArch64::TBZW:
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case AArch64::TBNZX:
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case AArch64::TBZX:
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return TBZDisplacementBits;
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case AArch64::CBNZW:
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case AArch64::CBZW:
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case AArch64::CBNZX:
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case AArch64::CBZX:
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return CBZDisplacementBits;
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case AArch64::Bcc:
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return BCCDisplacementBits;
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}
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}
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static inline void invertBccCondition(MachineInstr *MI) {
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assert(MI->getOpcode() == AArch64::Bcc && "Unexpected opcode!");
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AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm();
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CC = AArch64CC::getInvertedCondCode(CC);
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MI->getOperand(0).setImm((int64_t)CC);
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}
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/// fixupConditionalBranch - Fix up a conditional branch whose destination is
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/// too far away to fit in its displacement field. It is converted to an inverse
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/// conditional branch + an unconditional branch to the destination.
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bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr *MI) {
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MachineBasicBlock *DestBB = getDestBlock(MI);
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// Add an unconditional branch to the destination and invert the branch
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// condition to jump over it:
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// tbz L1
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// =>
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// tbnz L2
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// b L1
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// L2:
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// If the branch is at the end of its MBB and that has a fall-through block,
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// direct the updated conditional branch to the fall-through block. Otherwise,
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// split the MBB before the next instruction.
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MachineBasicBlock *MBB = MI->getParent();
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MachineInstr *BMI = &MBB->back();
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bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
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if (BMI != MI) {
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if (std::next(MachineBasicBlock::iterator(MI)) ==
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std::prev(MBB->getLastNonDebugInstr()) &&
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BMI->getOpcode() == AArch64::B) {
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// Last MI in the BB is an unconditional branch. Can we simply invert the
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// condition and swap destinations:
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// beq L1
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// b L2
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// =>
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// bne L2
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// b L1
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MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
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if (isBlockInRange(MI, NewDest,
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getBranchDisplacementBits(MI->getOpcode()))) {
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DEBUG(dbgs() << " Invert condition and swap its destination with "
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<< *BMI);
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BMI->getOperand(0).setMBB(DestBB);
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unsigned OpNum = (MI->getOpcode() == AArch64::TBZW ||
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MI->getOpcode() == AArch64::TBNZW ||
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MI->getOpcode() == AArch64::TBZX ||
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MI->getOpcode() == AArch64::TBNZX)
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? 2
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: 1;
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MI->getOperand(OpNum).setMBB(NewDest);
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MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode())));
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if (MI->getOpcode() == AArch64::Bcc)
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invertBccCondition(MI);
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return true;
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}
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}
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}
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if (NeedSplit) {
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// Analyze the branch so we know how to update the successor lists.
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MachineBasicBlock *TBB, *FBB;
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SmallVector<MachineOperand, 2> Cond;
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TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, false);
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MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI);
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// No need for the branch to the next block. We're adding an unconditional
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// branch to the destination.
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int delta = TII->GetInstSizeInBytes(&MBB->back());
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BlockInfo[MBB->getNumber()].Size -= delta;
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MBB->back().eraseFromParent();
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// BlockInfo[SplitBB].Offset is wrong temporarily, fixed below
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// Update the successor lists according to the transformation to follow.
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// Do it here since if there's no split, no update is needed.
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MBB->replaceSuccessor(FBB, NewBB);
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NewBB->addSuccessor(FBB);
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}
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MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(MBB));
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DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber()
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<< ", invert condition and change dest. to BB#"
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<< NextBB->getNumber() << "\n");
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// Insert a new conditional branch and a new unconditional branch.
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MachineInstrBuilder MIB = BuildMI(
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MBB, DebugLoc(), TII->get(getOppositeConditionOpcode(MI->getOpcode())))
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.addOperand(MI->getOperand(0));
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if (MI->getOpcode() == AArch64::TBZW || MI->getOpcode() == AArch64::TBNZW ||
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MI->getOpcode() == AArch64::TBZX || MI->getOpcode() == AArch64::TBNZX)
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MIB.addOperand(MI->getOperand(1));
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if (MI->getOpcode() == AArch64::Bcc)
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invertBccCondition(MIB);
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MIB.addMBB(NextBB);
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BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
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BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB);
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BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(&MBB->back());
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// Remove the old conditional branch. It may or may not still be in MBB.
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BlockInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(MI);
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MI->eraseFromParent();
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// Finally, keep the block offsets up to date.
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adjustBlockOffsets(*MBB);
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return true;
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}
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bool AArch64BranchRelaxation::relaxBranchInstructions() {
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bool Changed = false;
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// Relaxing branches involves creating new basic blocks, so re-eval
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// end() for termination.
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for (auto &MBB : *MF) {
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MachineInstr *MI = MBB.getFirstTerminator();
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if (isConditionalBranch(MI->getOpcode()) &&
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!isBlockInRange(MI, getDestBlock(MI),
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|
getBranchDisplacementBits(MI->getOpcode()))) {
|
|
fixupConditionalBranch(MI);
|
|
++NumRelaxed;
|
|
Changed = true;
|
|
}
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
bool AArch64BranchRelaxation::runOnMachineFunction(MachineFunction &mf) {
|
|
MF = &mf;
|
|
|
|
// If the pass is disabled, just bail early.
|
|
if (!BranchRelaxation)
|
|
return false;
|
|
|
|
DEBUG(dbgs() << "***** AArch64BranchRelaxation *****\n");
|
|
|
|
TII = (const AArch64InstrInfo *)MF->getTarget().getInstrInfo();
|
|
|
|
// Renumber all of the machine basic blocks in the function, guaranteeing that
|
|
// the numbers agree with the position of the block in the function.
|
|
MF->RenumberBlocks();
|
|
|
|
// Do the initial scan of the function, building up information about the
|
|
// sizes of each block.
|
|
scanFunction();
|
|
|
|
DEBUG(dbgs() << " Basic blocks before relaxation\n");
|
|
DEBUG(dumpBBs());
|
|
|
|
bool MadeChange = false;
|
|
while (relaxBranchInstructions())
|
|
MadeChange = true;
|
|
|
|
// After a while, this might be made debug-only, but it is not expensive.
|
|
verify();
|
|
|
|
DEBUG(dbgs() << " Basic blocks after relaxation\n");
|
|
DEBUG(dbgs() << '\n'; dumpBBs());
|
|
|
|
BlockInfo.clear();
|
|
|
|
return MadeChange;
|
|
}
|
|
|
|
/// createAArch64BranchRelaxation - returns an instance of the constpool
|
|
/// island pass.
|
|
FunctionPass *llvm::createAArch64BranchRelaxation() {
|
|
return new AArch64BranchRelaxation();
|
|
}
|