mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-29 10:32:47 +00:00
68db37b952
Now that compute support is better on SI, we can't continue using v16i8 for descriptors since this is also a legal type in OpenCL. This patch fixes numerous hangs with the piglit OpenCL test and since we now use a target specific DAG node for LOAD_CONSTANT with the correct MemOperandFlags, this should also fix: https://bugs.freedesktop.org/show_bug.cgi?id=66805 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188429 91177308-0d34-0410-b5e6-96231b3b80d8
141 lines
6.5 KiB
LLVM
141 lines
6.5 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 3
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 2
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 1
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 4
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 8
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 5
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 9
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 6
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 10
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 12
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 8
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define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
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%v2 = insertelement <4 x i32> undef, i32 %a1, i32 1
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%v3 = insertelement <4 x i32> undef, i32 %a1, i32 2
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%v4 = insertelement <4 x i32> undef, i32 %a1, i32 3
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%v5 = insertelement <4 x i32> undef, i32 %a2, i32 0
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%v6 = insertelement <4 x i32> undef, i32 %a2, i32 1
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%v7 = insertelement <4 x i32> undef, i32 %a2, i32 2
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%v8 = insertelement <4 x i32> undef, i32 %a2, i32 3
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%v9 = insertelement <4 x i32> undef, i32 %a3, i32 0
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%v10 = insertelement <4 x i32> undef, i32 %a3, i32 1
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%v11 = insertelement <4 x i32> undef, i32 %a3, i32 2
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%v12 = insertelement <4 x i32> undef, i32 %a3, i32 3
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%v13 = insertelement <4 x i32> undef, i32 %a4, i32 0
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%v14 = insertelement <4 x i32> undef, i32 %a4, i32 1
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%v15 = insertelement <4 x i32> undef, i32 %a4, i32 2
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%v16 = insertelement <4 x i32> undef, i32 %a4, i32 3
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%res1 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v1,
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<32 x i8> undef, <16 x i8> undef, i32 1)
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%res2 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v2,
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<32 x i8> undef, <16 x i8> undef, i32 2)
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%res3 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v3,
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<32 x i8> undef, <16 x i8> undef, i32 3)
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%res4 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v4,
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<32 x i8> undef, <16 x i8> undef, i32 4)
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%res5 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v5,
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<32 x i8> undef, <16 x i8> undef, i32 5)
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%res6 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v6,
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<32 x i8> undef, <16 x i8> undef, i32 6)
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%res7 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v7,
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<32 x i8> undef, <16 x i8> undef, i32 7)
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%res8 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v8,
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<32 x i8> undef, <16 x i8> undef, i32 8)
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%res9 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v9,
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<32 x i8> undef, <16 x i8> undef, i32 9)
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%res10 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v10,
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<32 x i8> undef, <16 x i8> undef, i32 10)
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%res11 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v11,
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<32 x i8> undef, <16 x i8> undef, i32 11)
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%res12 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v12,
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<32 x i8> undef, <16 x i8> undef, i32 12)
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%res13 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v13,
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<32 x i8> undef, <16 x i8> undef, i32 13)
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%res14 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v14,
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<32 x i8> undef, <16 x i8> undef, i32 14)
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%res15 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v15,
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<32 x i8> undef, <16 x i8> undef, i32 15)
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%res16 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v16,
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<32 x i8> undef, <16 x i8> undef, i32 16)
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%e1 = extractelement <4 x float> %res1, i32 0
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%e2 = extractelement <4 x float> %res2, i32 1
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%e3 = extractelement <4 x float> %res3, i32 2
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%e4 = extractelement <4 x float> %res4, i32 3
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%t0 = extractelement <4 x float> %res5, i32 0
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%t1 = extractelement <4 x float> %res5, i32 1
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%e5 = fadd float %t0, %t1
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%t2 = extractelement <4 x float> %res6, i32 0
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%t3 = extractelement <4 x float> %res6, i32 2
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%e6 = fadd float %t2, %t3
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%t4 = extractelement <4 x float> %res7, i32 0
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%t5 = extractelement <4 x float> %res7, i32 3
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%e7 = fadd float %t4, %t5
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%t6 = extractelement <4 x float> %res8, i32 1
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%t7 = extractelement <4 x float> %res8, i32 2
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%e8 = fadd float %t6, %t7
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%t8 = extractelement <4 x float> %res9, i32 1
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%t9 = extractelement <4 x float> %res9, i32 3
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%e9 = fadd float %t8, %t9
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%t10 = extractelement <4 x float> %res10, i32 2
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%t11 = extractelement <4 x float> %res10, i32 3
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%e10 = fadd float %t10, %t11
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%t12 = extractelement <4 x float> %res11, i32 0
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%t13 = extractelement <4 x float> %res11, i32 1
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%t14 = extractelement <4 x float> %res11, i32 2
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%t15 = fadd float %t12, %t13
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%e11 = fadd float %t14, %t15
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%t16 = extractelement <4 x float> %res12, i32 0
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%t17 = extractelement <4 x float> %res12, i32 1
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%t18 = extractelement <4 x float> %res12, i32 3
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%t19 = fadd float %t16, %t17
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%e12 = fadd float %t18, %t19
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%t20 = extractelement <4 x float> %res13, i32 0
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%t21 = extractelement <4 x float> %res13, i32 2
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%t22 = extractelement <4 x float> %res13, i32 3
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%t23 = fadd float %t20, %t21
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%e13 = fadd float %t22, %t23
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%t24 = extractelement <4 x float> %res14, i32 1
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%t25 = extractelement <4 x float> %res14, i32 2
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%t26 = extractelement <4 x float> %res14, i32 3
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%t27 = fadd float %t24, %t25
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%e14 = fadd float %t26, %t27
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%t28 = extractelement <4 x float> %res15, i32 0
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%t29 = extractelement <4 x float> %res15, i32 1
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%t30 = extractelement <4 x float> %res15, i32 2
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%t31 = extractelement <4 x float> %res15, i32 3
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%t32 = fadd float %t28, %t29
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%t33 = fadd float %t30, %t31
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%e15 = fadd float %t32, %t33
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%e16 = extractelement <4 x float> %res16, i32 3
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%s1 = fadd float %e1, %e2
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%s2 = fadd float %s1, %e3
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%s3 = fadd float %s2, %e4
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%s4 = fadd float %s3, %e5
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%s5 = fadd float %s4, %e6
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%s6 = fadd float %s5, %e7
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%s7 = fadd float %s6, %e8
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%s8 = fadd float %s7, %e9
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%s9 = fadd float %s8, %e10
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%s10 = fadd float %s9, %e11
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%s11 = fadd float %s10, %e12
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%s12 = fadd float %s11, %e13
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%s13 = fadd float %s12, %e14
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%s14 = fadd float %s13, %e15
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%s15 = fadd float %s14, %e16
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s15, float %s15, float %s15, float %s15)
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ret void
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}
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declare <4 x float> @llvm.SI.sampled.(<4 x i32>, <32 x i8>, <16 x i8>, i32) readnone
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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