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printing out assembly. After all, we want the real thing too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4783 91177308-0d34-0410-b5e6-96231b3b80d8
173 lines
5.3 KiB
C++
173 lines
5.3 KiB
C++
//===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
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//
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// This file contains a printer that converts from our internal representation
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// of LLVM code to a nice human readable form that is suitable for debuggging.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Function.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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namespace {
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struct Printer : public FunctionPass {
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TargetMachine &TM;
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std::ostream &O;
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Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
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bool runOnFunction(Function &F);
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};
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}
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/// createX86CodePrinterPass - Print out the specified machine code function to
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/// the specified stream. This function should work regardless of whether or
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/// not the function is in SSA form or not.
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///
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Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
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return new Printer(TM, O);
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}
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/// runOnFunction - This uses the X86InstructionInfo::print method
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/// to print assembly for each instruction.
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bool Printer::runOnFunction (Function & F)
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{
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static unsigned bbnumber = 0;
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MachineFunction & MF = MachineFunction::get (&F);
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const MachineInstrInfo & MII = TM.getInstrInfo ();
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O << "; x86 printing only sorta implemented so far!\n";
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// Print out labels for the function.
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O << "\t.globl\t" << F.getName () << "\n";
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O << "\t.type\t" << F.getName () << ", @function\n";
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O << F.getName () << ":\n";
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// Print out code for the function.
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for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
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bb_i != bb_e; ++bb_i)
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{
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// Print a label for the basic block.
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O << ".BB" << bbnumber++ << ":\n";
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for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
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bb_i->end (); i_i != i_e; ++i_i)
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{
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// Print the assembly for the instruction.
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O << "\t";
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MII.print(*i_i, O, TM);
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}
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}
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// We didn't modify anything.
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return false;
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}
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static void printOp(std::ostream &O, const MachineOperand &MO,
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const MRegisterInfo &RI) {
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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case MachineOperand::MO_MachineRegister:
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if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
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O << RI.get(MO.getReg()).Name;
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else
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O << "%reg" << MO.getReg();
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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}
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static inline void toHexDigit(std::ostream &O, unsigned char V) {
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if (V >= 10)
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O << (char)('A'+V-10);
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else
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O << (char)('0'+V);
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}
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static std::ostream &toHex(std::ostream &O, unsigned char V) {
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toHexDigit(O, V >> 4);
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toHexDigit(O, V & 0xF);
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return O;
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}
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// print - Print out an x86 instruction in intel syntax
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void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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const TargetMachine &TM) const {
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unsigned Opcode = MI->getOpcode();
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const MachineInstrDescriptor &Desc = get(Opcode);
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if (Desc.TSFlags & X86II::TB)
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O << "0F ";
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::OtherFrm:
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O << "\t";
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O << "-"; MI->print(O, TM);
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break;
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case X86II::RawFrm:
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toHex(O, getBaseOpcodeFor(Opcode)) << "\t";
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O << getName(MI->getOpCode()) << " ";
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (i) O << ", ";
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printOp(O, MI->getOperand(i), RI);
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}
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O << "\n";
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return;
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case X86II::AddRegFrm:
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O << "\t-"; MI->print(O, TM); break;
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case X86II::MRMDestReg:
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// There are two acceptable forms of MRMDestReg instructions, those with 3
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// and 2 operands:
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//
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// 3 Operands: in this form, the first two registers (the destination, and
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// the first operand) should be the same, post register allocation. The 3rd
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// operand is an additional input. This should be for things like add
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// instructions.
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//
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// 2 Operands: this is for things like mov that do not read a second input
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//
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assert(((MI->getNumOperands() == 3 &&
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(MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister||
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MI->getOperand(0).getType()==MachineOperand::MO_MachineRegister)
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&&
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(MI->getOperand(1).getType()==MachineOperand::MO_VirtualRegister||
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MI->getOperand(1).getType()==MachineOperand::MO_MachineRegister))
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||
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(MI->getNumOperands() == 2 &&
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(MI->getOperand(0).getType()==MachineOperand::MO_VirtualRegister||
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MI->getOperand(0).getType()==MachineOperand::MO_MachineRegister)
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&& (MI->getOperand(MI->getNumOperands()-1).getType() ==
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MachineOperand::MO_VirtualRegister||
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MI->getOperand(MI->getNumOperands()-1).getType() ==
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MachineOperand::MO_MachineRegister)))
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&& "Bad format for MRMDestReg!");
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if (MI->getNumOperands() == 3 &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << "\t";
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O << getName(MI->getOpCode()) << " ";
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printOp(O, MI->getOperand(0), RI);
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O << ", ";
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printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
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O << "\n";
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return;
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case X86II::MRMDestMem:
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case X86II::MRMSrcReg:
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case X86II::MRMSrcMem:
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default:
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O << "\t-"; MI->print(O, TM); break;
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}
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}
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