llvm-6502/arm64-fp-encoding-error.s at e1f835ab596a984f5d055ca98db375b72ddd7f14 - llvm-6502 - Applefritter: Git

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Tim Northover 112102c7fe AArch64: disallow "fmov sD, #-0.0" during assembly.

We weren't checking the sign of the floating point immediate before translating
it to "fmov sD, wzr". Similarly for D-regs.

Technically "movi vD.2s, #0x80, lsl #24" would work most of the time, but it's
not a blessed alias (and I don't think it should be since people expect writing
sD to zero out the high lanes, and there's no dD equivalent). So an error it is.

rdar://20455398

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234372 91177308-0d34-0410-b5e6-96231b3b80d8

2015-04-07 22:49:47 +00:00

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ArmAsm

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 ; RUN: not llvm-mc -triple arm64-apple-ios8.0 %s -o /dev/null 2>&1 | FileCheck %s
         fmov s0, #-0.0
 ; CHECK: error: expected compatible register or floating-point constant
         fmov d0, #-0.0
 ; CHECK: error: expected compatible register or floating-point constant