Dan Gohman bc0b56732a The list-td and list-tdrr schedulers don't yet support physreg ... scheduling dependencies. Add assertion checks to help catch this. It appears the Mips target defaults to list-td, and it has a regression test that uses a physreg dependence. Such code was liable to be miscompiled, and now evokes an assertion failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62177 91177308-0d34-0410-b5e6-96231b3b80d8		2009-01-13 20:24:13 +00:00
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Alpha
ARM	Clean up some ARM GV asm printing out; minor fixes to match what gcc does.	2008-12-06 02:00:55 +00:00
CBackend
CellSPU	Fix off-by-one error in traversing an array; this fixes a test.	2009-01-07 23:07:29 +00:00
CPP
Generic	The list-td and list-tdrr schedulers don't yet support physreg	2009-01-13 20:24:13 +00:00
IA64
Mips	The list-td and list-tdrr schedulers don't yet support physreg	2009-01-13 20:24:13 +00:00
PowerPC	this test should not run opt -std-compile-opts, it should run	2009-01-09 05:32:00 +00:00
SPARC
X86	When replacing uses and the same node is reached	2009-01-13 15:17:14 +00:00
XCore