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https://github.com/c64scene-ar/llvm-6502.git
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66e19c3e9d
llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156958 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.4 KiB
C++
69 lines
2.4 KiB
C++
//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Mips specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSubtarget.h"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "MipsGenSubtargetInfo.inc"
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using namespace llvm;
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void MipsSubtarget::anchor() { }
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MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool little) :
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MipsGenSubtargetInfo(TT, CPU, FS),
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MipsArchVersion(Mips32), MipsABI(UnknownABI), IsLittle(little),
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IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false),
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IsLinux(true), HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false),
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HasMinMax(false), HasSwap(false), HasBitCount(false), InMips16Mode(false)
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{
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "mips32";
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FS);
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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// Set MipsABI if it hasn't been set yet.
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if (MipsABI == UnknownABI)
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MipsABI = hasMips64() ? N64 : O32;
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// Check if Architecture and ABI are compatible.
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assert(((!hasMips64() && (isABI_O32() || isABI_EABI())) ||
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(hasMips64() && (isABI_N32() || isABI_N64()))) &&
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"Invalid Arch & ABI pair.");
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// Is the target system Linux ?
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if (TT.find("linux") == std::string::npos)
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IsLinux = false;
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}
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bool
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MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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TargetSubtargetInfo::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = TargetSubtargetInfo::ANTIDEP_NONE;
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(hasMips64() ?
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&Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass);
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return OptLevel >= CodeGenOpt::Aggressive;
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}
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