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information and update all callers. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
344 lines
12 KiB
C++
344 lines
12 KiB
C++
//===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the pass that finds instructions that can be
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// re-written as LEA instructions in order to reduce pipeline delays.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-fixup-LEAs"
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STATISTIC(NumLEAs, "Number of LEA instructions created");
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namespace {
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class FixupLEAPass : public MachineFunctionPass {
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enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
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static char ID;
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/// \brief Loop over all of the instructions in the basic block
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/// replacing applicable instructions with LEA instructions,
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/// where appropriate.
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bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI);
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const char *getPassName() const override { return "X86 LEA Fixup"; }
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/// \brief Given a machine register, look for the instruction
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/// which writes it in the current basic block. If found,
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/// try to replace it with an equivalent LEA instruction.
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/// If replacement succeeds, then also process the the newly created
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/// instruction.
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void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI);
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/// \brief Given a memory access or LEA instruction
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/// whose address mode uses a base and/or index register, look for
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/// an opportunity to replace the instruction which sets the base or index
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/// register with an equivalent LEA instruction.
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void processInstruction(MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI);
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/// \brief Given a LEA instruction which is unprofitable
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/// on Silvermont try to replace it with an equivalent ADD instruction
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void processInstructionForSLM(MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI);
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/// \brief Determine if an instruction references a machine register
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/// and, if so, whether it reads or writes the register.
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RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
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/// \brief Step backwards through a basic block, looking
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/// for an instruction which writes a register within
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/// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
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MachineBasicBlock::iterator searchBackwards(MachineOperand &p,
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MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI);
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/// \brief if an instruction can be converted to an
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/// equivalent LEA, insert the new instruction into the basic block
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/// and return a pointer to it. Otherwise, return zero.
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MachineInstr *postRAConvertToLEA(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI) const;
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public:
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FixupLEAPass() : MachineFunctionPass(ID) {}
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/// \brief Loop over all of the basic blocks,
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/// replacing instructions by equivalent LEA instructions
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/// if needed and when possible.
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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MachineFunction *MF;
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const TargetMachine *TM;
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const X86InstrInfo *TII; // Machine instruction info.
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};
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char FixupLEAPass::ID = 0;
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}
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MachineInstr *
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FixupLEAPass::postRAConvertToLEA(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI) const {
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MachineInstr *MI = MBBI;
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MachineInstr *NewMI;
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switch (MI->getOpcode()) {
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case X86::MOV32rr:
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case X86::MOV64rr: {
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const MachineOperand &Src = MI->getOperand(1);
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const MachineOperand &Dest = MI->getOperand(0);
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NewMI = BuildMI(*MF, MI->getDebugLoc(),
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TII->get(MI->getOpcode() == X86::MOV32rr ? X86::LEA32r
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: X86::LEA64r))
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.addOperand(Dest)
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.addOperand(Src)
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.addImm(1)
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.addReg(0)
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.addImm(0)
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.addReg(0);
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MFI->insert(MBBI, NewMI); // Insert the new inst
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return NewMI;
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}
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case X86::ADD64ri32:
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case X86::ADD64ri8:
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8_DB:
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case X86::ADD32ri:
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case X86::ADD32ri8:
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case X86::ADD32ri_DB:
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case X86::ADD32ri8_DB:
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri_DB:
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case X86::ADD16ri8_DB:
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if (!MI->getOperand(2).isImm()) {
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// convertToThreeAddress will call getImm()
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// which requires isImm() to be true
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return nullptr;
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}
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break;
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case X86::ADD16rr:
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case X86::ADD16rr_DB:
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if (MI->getOperand(1).getReg() != MI->getOperand(2).getReg()) {
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// if src1 != src2, then convertToThreeAddress will
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// need to create a Virtual register, which we cannot do
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// after register allocation.
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return nullptr;
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}
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}
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return TII->convertToThreeAddress(MFI, MBBI, nullptr);
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}
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FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
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bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) {
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MF = &Func;
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TM = &Func.getTarget();
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const X86Subtarget &ST = TM->getSubtarget<X86Subtarget>();
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if (!ST.LEAusesAG() && !ST.slowLEA())
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return false;
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TII =
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static_cast<const X86InstrInfo *>(TM->getSubtargetImpl()->getInstrInfo());
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DEBUG(dbgs() << "Start X86FixupLEAs\n";);
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// Process all basic blocks.
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for (MachineFunction::iterator I = Func.begin(), E = Func.end(); I != E; ++I)
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processBasicBlock(Func, I);
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DEBUG(dbgs() << "End X86FixupLEAs\n";);
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return true;
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}
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FixupLEAPass::RegUsageState
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FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
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RegUsageState RegUsage = RU_NotUsed;
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MachineInstr *MI = I;
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for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
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MachineOperand &opnd = MI->getOperand(i);
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if (opnd.isReg() && opnd.getReg() == p.getReg()) {
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if (opnd.isDef())
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return RU_Write;
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RegUsage = RU_Read;
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}
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}
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return RegUsage;
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}
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/// getPreviousInstr - Given a reference to an instruction in a basic
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/// block, return a reference to the previous instruction in the block,
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/// wrapping around to the last instruction of the block if the block
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/// branches to itself.
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static inline bool getPreviousInstr(MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI) {
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if (I == MFI->begin()) {
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if (MFI->isPredecessor(MFI)) {
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I = --MFI->end();
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return true;
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} else
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return false;
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}
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--I;
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return true;
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}
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MachineBasicBlock::iterator
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FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI) {
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int InstrDistance = 1;
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MachineBasicBlock::iterator CurInst;
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static const int INSTR_DISTANCE_THRESHOLD = 5;
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CurInst = I;
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bool Found;
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Found = getPreviousInstr(CurInst, MFI);
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while (Found && I != CurInst) {
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if (CurInst->isCall() || CurInst->isInlineAsm())
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break;
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if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
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break; // too far back to make a difference
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if (usesRegister(p, CurInst) == RU_Write) {
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return CurInst;
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}
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InstrDistance += TII->getInstrLatency(
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TM->getSubtargetImpl()->getInstrItineraryData(), CurInst);
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Found = getPreviousInstr(CurInst, MFI);
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}
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return nullptr;
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}
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void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI) {
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// Process a load, store, or LEA instruction.
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MachineInstr *MI = I;
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int opcode = MI->getOpcode();
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const MCInstrDesc &Desc = MI->getDesc();
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int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags, opcode);
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if (AddrOffset >= 0) {
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AddrOffset += X86II::getOperandBias(Desc);
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MachineOperand &p = MI->getOperand(AddrOffset + X86::AddrBaseReg);
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if (p.isReg() && p.getReg() != X86::ESP) {
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seekLEAFixup(p, I, MFI);
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}
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MachineOperand &q = MI->getOperand(AddrOffset + X86::AddrIndexReg);
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if (q.isReg() && q.getReg() != X86::ESP) {
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seekLEAFixup(q, I, MFI);
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}
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}
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}
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void FixupLEAPass::seekLEAFixup(MachineOperand &p,
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MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI) {
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MachineBasicBlock::iterator MBI = searchBackwards(p, I, MFI);
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if (MBI) {
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MachineInstr *NewMI = postRAConvertToLEA(MFI, MBI);
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if (NewMI) {
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++NumLEAs;
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DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
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// now to replace with an equivalent LEA...
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DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
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MFI->erase(MBI);
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MachineBasicBlock::iterator J =
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static_cast<MachineBasicBlock::iterator>(NewMI);
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processInstruction(J, MFI);
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}
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}
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}
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void FixupLEAPass::processInstructionForSLM(MachineBasicBlock::iterator &I,
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MachineFunction::iterator MFI) {
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MachineInstr *MI = I;
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const int opcode = MI->getOpcode();
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if (opcode != X86::LEA16r && opcode != X86::LEA32r && opcode != X86::LEA64r &&
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opcode != X86::LEA64_32r)
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return;
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if (MI->getOperand(5).getReg() != 0 || !MI->getOperand(4).isImm() ||
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!TII->isSafeToClobberEFLAGS(*MFI, I))
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return;
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const unsigned DstR = MI->getOperand(0).getReg();
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const unsigned SrcR1 = MI->getOperand(1).getReg();
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const unsigned SrcR2 = MI->getOperand(3).getReg();
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if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
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return;
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if (MI->getOperand(2).getImm() > 1)
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return;
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int addrr_opcode, addri_opcode;
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switch (opcode) {
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case X86::LEA16r:
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addrr_opcode = X86::ADD16rr;
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addri_opcode = X86::ADD16ri;
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break;
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case X86::LEA32r:
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addrr_opcode = X86::ADD32rr;
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addri_opcode = X86::ADD32ri;
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break;
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case X86::LEA64_32r:
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case X86::LEA64r:
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addrr_opcode = X86::ADD64rr;
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addri_opcode = X86::ADD64ri32;
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break;
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default:
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assert(false && "Unexpected LEA instruction");
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}
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DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
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DEBUG(dbgs() << "FixLEA: Replaced by: ";);
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MachineInstr *NewMI = nullptr;
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const MachineOperand &Dst = MI->getOperand(0);
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// Make ADD instruction for two registers writing to LEA's destination
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if (SrcR1 != 0 && SrcR2 != 0) {
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const MachineOperand &Src1 = MI->getOperand(SrcR1 == DstR ? 1 : 3);
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const MachineOperand &Src2 = MI->getOperand(SrcR1 == DstR ? 3 : 1);
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NewMI = BuildMI(*MF, MI->getDebugLoc(), TII->get(addrr_opcode))
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.addOperand(Dst)
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.addOperand(Src1)
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.addOperand(Src2);
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MFI->insert(I, NewMI);
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DEBUG(NewMI->dump(););
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}
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// Make ADD instruction for immediate
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if (MI->getOperand(4).getImm() != 0) {
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const MachineOperand &SrcR = MI->getOperand(SrcR1 == DstR ? 1 : 3);
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NewMI = BuildMI(*MF, MI->getDebugLoc(), TII->get(addri_opcode))
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.addOperand(Dst)
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.addOperand(SrcR)
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.addImm(MI->getOperand(4).getImm());
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MFI->insert(I, NewMI);
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DEBUG(NewMI->dump(););
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}
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if (NewMI) {
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MFI->erase(I);
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I = static_cast<MachineBasicBlock::iterator>(NewMI);
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}
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}
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bool FixupLEAPass::processBasicBlock(MachineFunction &MF,
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MachineFunction::iterator MFI) {
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for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
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if (TM->getSubtarget<X86Subtarget>().isSLM())
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processInstructionForSLM(I, MFI);
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else
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processInstruction(I, MFI);
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}
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return false;
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}
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