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36ba909184
v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174632 91177308-0d34-0410-b5e6-96231b3b80d8
269 lines
9.2 KiB
TableGen
269 lines
9.2 KiB
TableGen
//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction defs that are common to all hw codegen
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// targets.
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//
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//===----------------------------------------------------------------------===//
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class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
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field bit isRegisterLoad = 0;
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field bit isRegisterStore = 0;
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let Namespace = "AMDGPU";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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let Itinerary = NullALU;
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let TSFlags{63} = isRegisterLoad;
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let TSFlags{62} = isRegisterStore;
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}
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class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
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: AMDGPUInst<outs, ins, asm, pattern> {
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field bits<32> Inst = 0xffffffff;
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}
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def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
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def COND_EQ : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOEQ: case ISD::SETUEQ:
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case ISD::SETEQ: return true;}}}]
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>;
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def COND_NE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETONE: case ISD::SETUNE:
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case ISD::SETNE: return true;}}}]
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>;
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def COND_GT : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOGT: case ISD::SETUGT:
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case ISD::SETGT: return true;}}}]
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>;
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def COND_GE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOGE: case ISD::SETUGE:
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case ISD::SETGE: return true;}}}]
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>;
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def COND_LT : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOLT: case ISD::SETULT:
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case ISD::SETLT: return true;}}}]
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>;
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def COND_LE : PatLeaf <
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(cond),
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[{switch(N->get()){{default: return false;
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case ISD::SETOLE: case ISD::SETULE:
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case ISD::SETLE: return true;}}}]
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>;
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//===----------------------------------------------------------------------===//
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// Load/Store Pattern Fragments
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//===----------------------------------------------------------------------===//
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def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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class Constants {
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int TWO_PI = 0x40c90fdb;
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int PI = 0x40490fdb;
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int TWO_PI_INV = 0x3e22f983;
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}
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def CONST : Constants;
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def FP_ZERO : PatLeaf <
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(fpimm),
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[{return N->getValueAPF().isZero();}]
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>;
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def FP_ONE : PatLeaf <
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(fpimm),
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[{return N->isExactlyValue(1.0);}]
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>;
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let isCodeGenOnly = 1, isPseudo = 1 in {
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let usesCustomInserter = 1 in {
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class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"CLAMP $dst, $src0",
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[(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
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>;
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class FABS <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FABS $dst, $src0",
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[(set rc:$dst, (fabs rc:$src0))]
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>;
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class FNEG <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FNEG $dst, $src0",
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[(set rc:$dst, (fneg rc:$src0))]
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>;
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def SHADER_TYPE : AMDGPUShaderInst <
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(outs),
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(ins i32imm:$type),
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"SHADER_TYPE $type",
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[(int_AMDGPU_shader_type imm:$type)]
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>;
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} // usesCustomInserter = 1
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multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
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ComplexPattern addrPat> {
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def RegisterLoad : AMDGPUShaderInst <
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(outs dstClass:$dst),
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(ins addrClass:$addr, i32imm:$chan),
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"RegisterLoad $dst, $addr",
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[(set (i32 dstClass:$dst), (AMDGPUregister_load addrPat:$addr,
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(i32 timm:$chan)))]
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> {
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let isRegisterLoad = 1;
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}
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def RegisterStore : AMDGPUShaderInst <
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(outs),
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(ins dstClass:$val, addrClass:$addr, i32imm:$chan),
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"RegisterStore $val, $addr",
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[(AMDGPUregister_store (i32 dstClass:$val), addrPat:$addr, (i32 timm:$chan))]
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> {
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let isRegisterStore = 1;
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}
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}
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} // End isCodeGenOnly = 1, isPseudo = 1
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/* Generic helper patterns for intrinsics */
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/* -------------------------------------- */
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class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
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RegisterClass rc> : Pat <
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(fpow rc:$src0, rc:$src1),
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(exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
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>;
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/* Other helper patterns */
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/* --------------------- */
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/* Extract element pattern */
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class Extract_Element <ValueType sub_type, ValueType vec_type,
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RegisterClass vec_class, int sub_idx,
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SubRegIndex sub_reg>: Pat<
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(sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
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(EXTRACT_SUBREG vec_class:$src, sub_reg)
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>;
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/* Insert element pattern */
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class Insert_Element <ValueType elem_type, ValueType vec_type,
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RegisterClass elem_class, RegisterClass vec_class,
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int sub_idx, SubRegIndex sub_reg> : Pat <
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(vec_type (vector_insert (vec_type vec_class:$vec),
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(elem_type elem_class:$elem), sub_idx)),
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(INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
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>;
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// Vector Build pattern
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class Vector1_Build <ValueType vecType, RegisterClass vectorClass,
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ValueType elemType, RegisterClass elemClass> : Pat <
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(vecType (build_vector (elemType elemClass:$src))),
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(vecType elemClass:$src)
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>;
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class Vector2_Build <ValueType vecType, RegisterClass vectorClass,
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ValueType elemType, RegisterClass elemClass> : Pat <
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(vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1))),
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(INSERT_SUBREG (INSERT_SUBREG
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(vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1)
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>;
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class Vector_Build <ValueType vecType, RegisterClass vectorClass,
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ValueType elemType, RegisterClass elemClass> : Pat <
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(vecType (build_vector (elemType elemClass:$x), (elemType elemClass:$y),
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(elemType elemClass:$z), (elemType elemClass:$w))),
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(vecType (IMPLICIT_DEF)), elemClass:$x, sub0), elemClass:$y, sub1),
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elemClass:$z, sub2), elemClass:$w, sub3)
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>;
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class Vector8_Build <ValueType vecType, RegisterClass vectorClass,
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ValueType elemType, RegisterClass elemClass> : Pat <
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(vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
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(elemType elemClass:$sub2), (elemType elemClass:$sub3),
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(elemType elemClass:$sub4), (elemType elemClass:$sub5),
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(elemType elemClass:$sub6), (elemType elemClass:$sub7))),
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1),
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elemClass:$sub2, sub2), elemClass:$sub3, sub3),
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elemClass:$sub4, sub4), elemClass:$sub5, sub5),
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elemClass:$sub6, sub6), elemClass:$sub7, sub7)
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>;
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class Vector16_Build <ValueType vecType, RegisterClass vectorClass,
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ValueType elemType, RegisterClass elemClass> : Pat <
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(vecType (build_vector (elemType elemClass:$sub0), (elemType elemClass:$sub1),
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(elemType elemClass:$sub2), (elemType elemClass:$sub3),
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(elemType elemClass:$sub4), (elemType elemClass:$sub5),
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(elemType elemClass:$sub6), (elemType elemClass:$sub7),
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(elemType elemClass:$sub8), (elemType elemClass:$sub9),
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(elemType elemClass:$sub10), (elemType elemClass:$sub11),
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(elemType elemClass:$sub12), (elemType elemClass:$sub13),
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(elemType elemClass:$sub14), (elemType elemClass:$sub15))),
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG
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(vecType (IMPLICIT_DEF)), elemClass:$sub0, sub0), elemClass:$sub1, sub1),
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elemClass:$sub2, sub2), elemClass:$sub3, sub3),
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elemClass:$sub4, sub4), elemClass:$sub5, sub5),
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elemClass:$sub6, sub6), elemClass:$sub7, sub7),
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elemClass:$sub8, sub8), elemClass:$sub9, sub9),
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elemClass:$sub10, sub10), elemClass:$sub11, sub11),
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elemClass:$sub12, sub12), elemClass:$sub13, sub13),
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elemClass:$sub14, sub14), elemClass:$sub15, sub15)
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>;
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// bitconvert pattern
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class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
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(dt (bitconvert (st rc:$src0))),
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(dt rc:$src0)
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>;
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class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
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(vt (AMDGPUdwordaddr (vt rc:$addr))),
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(vt rc:$addr)
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>;
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include "R600Instructions.td"
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include "SIInstrInfo.td"
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