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https://github.com/c64scene-ar/llvm-6502.git
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2ee746b87d
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes. The DAGCombiner has two optimizations that can mitigate the problem. First, if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT nodes, then it is possible to create a new simplified BUILD_VECTOR which uses UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes. Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle vector instruction. In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be shuffled into a wide YMM register. This patch modifes the second optimization and allows the creation of shuffle vectors even when the newly generated vector and the original vector from which we extract the values are of different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150340 91177308-0d34-0410-b5e6-96231b3b80d8
173 lines
6.2 KiB
LLVM
173 lines
6.2 KiB
LLVM
; RUN: llc < %s -march=cellspu -o %t1.s
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; RUN: grep rot %t1.s | count 86
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; RUN: grep roth %t1.s | count 8
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; RUN: grep roti.*5 %t1.s | count 1
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; RUN: grep roti.*27 %t1.s | count 1
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; RUN: grep rothi.*5 %t1.s | count 2
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; RUN: grep rothi.*11 %t1.s | count 1
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; RUN: grep rothi.*,.3 %t1.s | count 1
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; RUN: grep andhi %t1.s | count 4
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; RUN: grep shlhi %t1.s | count 4
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; RUN: cat %t1.s | FileCheck %s
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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; Vector rotates are not currently supported in gcc or llvm assembly. These are
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; not tested.
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; 32-bit rotates:
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define i32 @rotl32_1a(i32 %arg1, i8 %arg2) {
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%tmp1 = zext i8 %arg2 to i32 ; <i32> [#uses=1]
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%B = shl i32 %arg1, %tmp1 ; <i32> [#uses=1]
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%arg22 = sub i8 32, %arg2 ; <i8> [#uses=1]
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%tmp2 = zext i8 %arg22 to i32 ; <i32> [#uses=1]
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%C = lshr i32 %arg1, %tmp2 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotl32_1b(i32 %arg1, i16 %arg2) {
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%tmp1 = zext i16 %arg2 to i32 ; <i32> [#uses=1]
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%B = shl i32 %arg1, %tmp1 ; <i32> [#uses=1]
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%arg22 = sub i16 32, %arg2 ; <i8> [#uses=1]
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%tmp2 = zext i16 %arg22 to i32 ; <i32> [#uses=1]
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%C = lshr i32 %arg1, %tmp2 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotl32_2(i32 %arg1, i32 %arg2) {
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%B = shl i32 %arg1, %arg2 ; <i32> [#uses=1]
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%tmp1 = sub i32 32, %arg2 ; <i32> [#uses=1]
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%C = lshr i32 %arg1, %tmp1 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotl32_3(i32 %arg1, i32 %arg2) {
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%tmp1 = sub i32 32, %arg2 ; <i32> [#uses=1]
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%B = shl i32 %arg1, %arg2 ; <i32> [#uses=1]
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%C = lshr i32 %arg1, %tmp1 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotl32_4(i32 %arg1, i32 %arg2) {
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%tmp1 = sub i32 32, %arg2 ; <i32> [#uses=1]
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%C = lshr i32 %arg1, %tmp1 ; <i32> [#uses=1]
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%B = shl i32 %arg1, %arg2 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotr32_1(i32 %A, i8 %Amt) {
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%tmp1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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%B = lshr i32 %A, %tmp1 ; <i32> [#uses=1]
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%Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
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%tmp2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
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%C = shl i32 %A, %tmp2 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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define i32 @rotr32_2(i32 %A, i8 %Amt) {
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%Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
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%tmp1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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%B = lshr i32 %A, %tmp1 ; <i32> [#uses=1]
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%tmp2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1]
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%C = shl i32 %A, %tmp2 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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; Rotate left with immediate
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define i32 @rotli32(i32 %A) {
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%B = shl i32 %A, 5 ; <i32> [#uses=1]
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%C = lshr i32 %A, 27 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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; Rotate right with immediate
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define i32 @rotri32(i32 %A) {
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%B = lshr i32 %A, 5 ; <i32> [#uses=1]
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%C = shl i32 %A, 27 ; <i32> [#uses=1]
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%D = or i32 %B, %C ; <i32> [#uses=1]
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ret i32 %D
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}
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; 16-bit rotates:
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define i16 @rotr16_1(i16 %arg1, i8 %arg) {
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%tmp1 = zext i8 %arg to i16 ; <i16> [#uses=1]
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%B = lshr i16 %arg1, %tmp1 ; <i16> [#uses=1]
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%arg2 = sub i8 16, %arg ; <i8> [#uses=1]
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%tmp2 = zext i8 %arg2 to i16 ; <i16> [#uses=1]
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%C = shl i16 %arg1, %tmp2 ; <i16> [#uses=1]
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%D = or i16 %B, %C ; <i16> [#uses=1]
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ret i16 %D
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}
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define i16 @rotr16_2(i16 %arg1, i16 %arg) {
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%B = lshr i16 %arg1, %arg ; <i16> [#uses=1]
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%tmp1 = sub i16 16, %arg ; <i16> [#uses=1]
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%C = shl i16 %arg1, %tmp1 ; <i16> [#uses=1]
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%D = or i16 %B, %C ; <i16> [#uses=1]
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ret i16 %D
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}
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define i16 @rotli16(i16 %A) {
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%B = shl i16 %A, 5 ; <i16> [#uses=1]
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%C = lshr i16 %A, 11 ; <i16> [#uses=1]
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%D = or i16 %B, %C ; <i16> [#uses=1]
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ret i16 %D
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}
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define i16 @rotri16(i16 %A) {
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%B = lshr i16 %A, 5 ; <i16> [#uses=1]
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%C = shl i16 %A, 11 ; <i16> [#uses=1]
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%D = or i16 %B, %C ; <i16> [#uses=1]
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ret i16 %D
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}
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define i8 @rotl8(i8 %A, i8 %Amt) {
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%B = shl i8 %A, %Amt ; <i8> [#uses=1]
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%Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
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%C = lshr i8 %A, %Amt2 ; <i8> [#uses=1]
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%D = or i8 %B, %C ; <i8> [#uses=1]
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ret i8 %D
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}
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define i8 @rotr8(i8 %A, i8 %Amt) {
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%B = lshr i8 %A, %Amt ; <i8> [#uses=1]
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%Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
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%C = shl i8 %A, %Amt2 ; <i8> [#uses=1]
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%D = or i8 %B, %C ; <i8> [#uses=1]
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ret i8 %D
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}
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define i8 @rotli8(i8 %A) {
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%B = shl i8 %A, 5 ; <i8> [#uses=1]
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%C = lshr i8 %A, 3 ; <i8> [#uses=1]
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%D = or i8 %B, %C ; <i8> [#uses=1]
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ret i8 %D
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}
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define i8 @rotri8(i8 %A) {
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%B = lshr i8 %A, 5 ; <i8> [#uses=1]
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%C = shl i8 %A, 3 ; <i8> [#uses=1]
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%D = or i8 %B, %C ; <i8> [#uses=1]
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ret i8 %D
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}
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define <2 x float> @test1(<4 x float> %param )
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{
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; CHECK: test1
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; CHECK: shufb
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%el = extractelement <4 x float> %param, i32 1
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%vec1 = insertelement <1 x float> undef, float %el, i32 0
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%rv = shufflevector <1 x float> %vec1, <1 x float> undef, <2 x i32><i32 0,i32 0>
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; CHECK: bi $lr
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ret <2 x float> %rv
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}
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