mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e88d5cee9d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
838 lines
33 KiB
TableGen
838 lines
33 KiB
TableGen
//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Thumb2 instruction set.
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//
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//===----------------------------------------------------------------------===//
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// Shifted operands. No register controlled shifts for Thumb2.
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// Note: We do not support rrx shifted operands yet.
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def t2_so_reg : Operand<i32>, // reg imm
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ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
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[shl,srl,sra,rotr]> {
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let PrintMethod = "printT2SOOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
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// described for t2_so_imm def below.
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def t2_so_imm_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
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}]>;
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// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
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def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
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}]>;
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// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
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def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
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}]>;
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// t2_so_imm - Match a 32-bit immediate operand, which is an
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// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
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// immediate splatted into multiple bytes of the word. t2_so_imm values are
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// represented in the imm field in the same 12-bit form that they are encoded
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// into t2_so_imm instructions: the 8-bit immediate is the least significant bits
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// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
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def t2_so_imm : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
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}], t2_so_imm_XFORM> {
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let PrintMethod = "printT2SOImmOperand";
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}
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// t2_so_imm_not - Match an immediate that is a complement
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// of a t2_so_imm.
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def t2_so_imm_not : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
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}], t2_so_imm_not_XFORM> {
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let PrintMethod = "printT2SOImmOperand";
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}
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// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
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def t2_so_imm_neg : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
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}], t2_so_imm_neg_XFORM> {
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let PrintMethod = "printT2SOImmOperand";
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}
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/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
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def imm1_31 : PatLeaf<(i32 imm), [{
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return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
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}]>;
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/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
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def imm0_4095 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 4096;
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}]>;
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def imm0_4095_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)(-N->getZExtValue()) < 4096;
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}], imm_neg_XFORM>;
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/// imm0_65535 predicate - True if the 32-bit immediate is in the range
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/// [0.65535].
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def imm0_65535 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 65536;
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}]>;
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/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
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/// e.g., 0xf000ffff
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def bf_inv_mask_imm : Operand<i32>,
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PatLeaf<(imm), [{
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uint32_t v = (uint32_t)N->getZExtValue();
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if (v == 0xffffffff)
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return 0;
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// naive checker. should do better, but simple is best for now since it's
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// more likely to be correct.
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while (v & 1) v >>= 1; // shift off the leading 1's
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if (v)
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{
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while (!(v & 1)) v >>=1; // shift off the mask
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while (v & 1) v >>= 1; // shift off the trailing 1's
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}
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// if this is a mask for clearing a bitfield, what's left should be zero.
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return (v == 0);
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}] > {
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let PrintMethod = "printBitfieldInvMaskImmOperand";
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}
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/// Split a 32-bit immediate into two 16 bit parts.
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def t2_lo16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
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MVT::i32);
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}]>;
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def t2_hi16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
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}]>;
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def t2_lo16AllZero : PatLeaf<(i32 imm), [{
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// Returns true if all low 16-bits are 0.
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return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
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}], t2_hi16>;
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// Define Thumb2 specific addressing modes.
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// t2addrmode_imm12 := reg + imm12
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def t2addrmode_imm12 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
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let PrintMethod = "printT2AddrModeImm12Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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// t2addrmode_imm8 := reg - imm8
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def t2addrmode_imm8 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
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let PrintMethod = "printT2AddrModeImm8Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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def t2am_imm8_offset : Operand<i32> {
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let PrintMethod = "printT2AddrModeImm8OffsetOperand";
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}
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// t2addrmode_imm8s4 := reg + (imm8 << 2)
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def t2addrmode_imm8s4 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
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let PrintMethod = "printT2AddrModeImm8Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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// t2addrmode_so_reg := reg + reg << imm2
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def t2addrmode_so_reg : Operand<i32>,
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ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
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let PrintMethod = "printT2AddrModeSoRegOperand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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//===----------------------------------------------------------------------===//
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// Multiclass helpers...
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//
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/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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/// unary operation that produces a value. These are predicable and can be
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/// changed to modify CPSR.
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multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
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// shifted imm
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def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
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opc, " $dst, $src",
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[(set GPR:$dst, (opnode t2_so_imm:$src))]> {
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let isAsCheapAsAMove = Cheap;
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let isReMaterializable = ReMat;
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}
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// register
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def r : T2I<(outs GPR:$dst), (ins GPR:$src),
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opc, " $dst, $src",
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[(set GPR:$dst, (opnode GPR:$src))]>;
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// shifted register
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def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
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opc, " $dst, $src",
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[(set GPR:$dst, (opnode t2_so_reg:$src))]>;
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}
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/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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// binary operation that produces a value. These are predicable and can be
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/// changed to modify CPSR.
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multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> {
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// shifted imm
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def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// register
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def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
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let isCommutable = Commutable;
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}
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// shifted register
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def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
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/// reversed. It doesn't define the 'rr' form since it's handled by its
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/// T2I_bin_irs counterpart.
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multiclass T2I_rbin_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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opc, " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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opc, " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
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}
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/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
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/// instruction modifies the CPSR register.
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let Defs = [CPSR] in {
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multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, "s"), " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// register
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def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, "s"), " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
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let isCommutable = Commutable;
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}
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, "s"), " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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}
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/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
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/// patterns for a binary operation that produces a value.
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multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
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// shifted imm
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def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// 12-bit imm
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def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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!strconcat(opc, "w"), " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
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// register
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def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
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let isCommutable = Commutable;
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}
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// shifted register
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def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
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/// binary operation that produces a value and use and define the carry bit.
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/// It's not predicable.
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let Uses = [CPSR] in {
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multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
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// shifted imm
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def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUnused]>;
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// register
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def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUnused]> {
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let isCommutable = Commutable;
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}
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// shifted register
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def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUnused]>;
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// Carry setting variants
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// shifted imm
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def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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// register
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def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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let isCommutable = Commutable;
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}
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// shifted register
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def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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}
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}
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/// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are
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/// reversed. It doesn't define the 'rr' form since it's handled by its
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/// T2I_adde_sube_irs counterpart.
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let Defs = [CPSR], Uses = [CPSR] in {
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multiclass T2I_rsc_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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opc, " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUnused]>;
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// shifted register
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def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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opc, " $dst, $rhs, $lhs",
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUnused]>;
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// shifted imm
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def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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!strconcat(opc, "s $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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// shifted register
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def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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!strconcat(opc, "s $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>,
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Requires<[IsThumb2, CarryDefIsUsed]> {
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let Defs = [CPSR];
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}
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}
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}
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/// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are
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/// reversed. It doesn't define the 'rr' form since it's handled by its
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/// T2I_bin_s_irs counterpart.
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let Defs = [CPSR] in {
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multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
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!strconcat(opc, "${s} $dst, $rhs, $lhs"),
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
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}
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}
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/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
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// rotate operation that produces a value.
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multiclass T2I_sh_ir<string opc, PatFrag opnode> {
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// 5-bit imm
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def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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opc, " $dst, $lhs, $rhs",
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[(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
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// register
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|
def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
|
|
opc, " $dst, $lhs, $rhs",
|
|
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
|
|
}
|
|
|
|
/// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
|
|
/// patterns. Similar to T2I_bin_irs except the instruction does not produce
|
|
/// a explicit result, only implicitly set CPSR.
|
|
let Uses = [CPSR] in {
|
|
multiclass T2I_cmp_is<string opc, PatFrag opnode> {
|
|
// shifted imm
|
|
def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
|
|
opc, " $lhs, $rhs",
|
|
[(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
|
|
// register
|
|
def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
|
|
opc, " $lhs, $rhs",
|
|
[(opnode GPR:$lhs, GPR:$rhs)]>;
|
|
// shifted register
|
|
def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
|
|
opc, " $lhs, $rhs",
|
|
[(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
|
|
}
|
|
}
|
|
|
|
/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
|
|
multiclass T2I_ld<string opc, PatFrag opnode> {
|
|
def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr),
|
|
opc, " $dst, $addr",
|
|
[(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
|
|
def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr),
|
|
opc, " $dst, $addr",
|
|
[(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
|
|
def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr),
|
|
opc, " $dst, $addr",
|
|
[(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
|
|
def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr),
|
|
opc, " $dst, $addr",
|
|
[(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
|
|
}
|
|
|
|
/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
|
|
multiclass T2I_st<string opc, PatFrag opnode> {
|
|
def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr),
|
|
opc, " $src, $addr",
|
|
[(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
|
|
def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr),
|
|
opc, " $src, $addr",
|
|
[(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
|
|
def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr),
|
|
opc, " $src, $addr",
|
|
[(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
|
|
}
|
|
|
|
/// T2I_picld - Defines the PIC load pattern.
|
|
class T2I_picld<string opc, PatFrag opnode> :
|
|
T2I<(outs GPR:$dst), (ins addrmodepc:$addr),
|
|
!strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
|
|
[(set GPR:$dst, (opnode addrmodepc:$addr))]>;
|
|
|
|
/// T2I_picst - Defines the PIC store pattern.
|
|
class T2I_picst<string opc, PatFrag opnode> :
|
|
T2I<(outs), (ins GPR:$src, addrmodepc:$addr),
|
|
!strconcat("${addr:label}:\n\t", opc), " $src, $addr",
|
|
[(opnode GPR:$src, addrmodepc:$addr)]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Miscellaneous Instructions.
|
|
//
|
|
|
|
let isNotDuplicable = 1 in
|
|
def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
|
|
"$cp:\n\tadd $dst, pc",
|
|
[(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
|
|
|
|
|
|
// LEApcrel - Load a pc-relative address into a register without offending the
|
|
// assembler.
|
|
def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
|
|
"${:private}PCRELL${:uid}+8))\n"),
|
|
!strconcat("${:private}PCRELL${:uid}:\n\t",
|
|
"add$p $dst, pc, #PCRELV${:uid}")),
|
|
[]>;
|
|
|
|
def t2LEApcrelJT : T2XI<(outs GPR:$dst),
|
|
(ins i32imm:$label, i32imm:$id, pred:$p),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
|
|
"${:private}PCRELL${:uid}+8))\n"),
|
|
!strconcat("${:private}PCRELL${:uid}:\n\t",
|
|
"add$p $dst, pc, #PCRELV${:uid}")),
|
|
[]>;
|
|
|
|
// ADD rd, sp, #so_imm
|
|
def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
|
|
"add $dst, $sp, $imm",
|
|
[]>;
|
|
|
|
// ADD rd, sp, #imm12
|
|
def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
|
|
"addw $dst, $sp, $imm",
|
|
[]>;
|
|
|
|
def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
|
|
"addw $dst, $sp, $rhs",
|
|
[]>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Load / store Instructions.
|
|
//
|
|
|
|
// Load
|
|
let canFoldAsLoad = 1 in
|
|
defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
|
|
|
|
// Loads with zero extension
|
|
defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
|
|
defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
|
|
|
|
// Loads with sign extension
|
|
defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
|
|
defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
|
|
|
|
let mayLoad = 1 in {
|
|
// Load doubleword
|
|
def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
|
|
"ldrd", " $dst, $addr", []>;
|
|
def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr),
|
|
"ldrd", " $dst, $addr", []>;
|
|
}
|
|
|
|
// zextload i1 -> zextload i8
|
|
def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
|
|
(t2LDRBi12 t2addrmode_imm12:$addr)>;
|
|
def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
|
|
(t2LDRBi8 t2addrmode_imm8:$addr)>;
|
|
def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
|
|
(t2LDRBs t2addrmode_so_reg:$addr)>;
|
|
def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
|
|
(t2LDRBpci tconstpool:$addr)>;
|
|
|
|
// extload -> zextload
|
|
// FIXME: Reduce the number of patterns by legalizing extload to zextload
|
|
// earlier?
|
|
def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
|
|
(t2LDRBi12 t2addrmode_imm12:$addr)>;
|
|
def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
|
|
(t2LDRBi8 t2addrmode_imm8:$addr)>;
|
|
def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
|
|
(t2LDRBs t2addrmode_so_reg:$addr)>;
|
|
def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
|
|
(t2LDRBpci tconstpool:$addr)>;
|
|
|
|
def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
|
|
(t2LDRBi12 t2addrmode_imm12:$addr)>;
|
|
def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
|
|
(t2LDRBi8 t2addrmode_imm8:$addr)>;
|
|
def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
|
|
(t2LDRBs t2addrmode_so_reg:$addr)>;
|
|
def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
|
|
(t2LDRBpci tconstpool:$addr)>;
|
|
|
|
def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
|
|
(t2LDRHi12 t2addrmode_imm12:$addr)>;
|
|
def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
|
|
(t2LDRHi8 t2addrmode_imm8:$addr)>;
|
|
def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
|
|
(t2LDRHs t2addrmode_so_reg:$addr)>;
|
|
def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
|
|
(t2LDRHpci tconstpool:$addr)>;
|
|
|
|
// Indexed loads
|
|
def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins t2addrmode_imm8:$addr),
|
|
AddrModeT2_i8, IndexModePre,
|
|
"ldr", " $dst, $addr!", "$addr.base = $base_wb",
|
|
[]>;
|
|
|
|
def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base, t2am_imm8_offset:$offset),
|
|
AddrModeT2_i8, IndexModePost,
|
|
"ldr", " $dst, [$base], $offset", "$base = $base_wb",
|
|
[]>;
|
|
|
|
def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins t2addrmode_imm8:$addr),
|
|
AddrModeT2_i8, IndexModePre,
|
|
"ldrb", " $dst, $addr!", "$addr.base = $base_wb",
|
|
[]>;
|
|
def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base, t2am_imm8_offset:$offset),
|
|
AddrModeT2_i8, IndexModePost,
|
|
"ldrb", " $dst, [$base], $offset", "$base = $base_wb",
|
|
[]>;
|
|
|
|
def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins t2addrmode_imm8:$addr),
|
|
AddrModeT2_i8, IndexModePre,
|
|
"ldrh", " $dst, $addr!", "$addr.base = $base_wb",
|
|
[]>;
|
|
def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
|
|
(ins GPR:$base, t2am_imm8_offset:$offset),
|
|
AddrModeT2_i8, IndexModePost,
|
|
"ldrh", " $dst, [$base], $offset", "$base = $base_wb",
|
|
[]>;
|
|
|
|
// Store
|
|
defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
|
|
defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
|
|
defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
|
|
|
|
// Store doubleword
|
|
let mayLoad = 1 in
|
|
def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
|
|
"strd", " $src, $addr", []>;
|
|
|
|
|
|
// Address computation and loads and stores in PIC mode.
|
|
let isNotDuplicable = 1, AddedComplexity = 10 in {
|
|
let canFoldAsLoad = 1 in
|
|
def t2PICLDR : T2I_picld<"ldr", UnOpFrag<(load node:$Src)>>;
|
|
|
|
def t2PICLDRH : T2I_picld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
|
|
def t2PICLDRB : T2I_picld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
|
|
def t2PICLDRSH : T2I_picld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
|
|
def t2PICLDRSB : T2I_picld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
|
|
|
|
def t2PICSTR : T2I_picst<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
|
|
def t2PICSTRH : T2I_picst<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
|
|
def t2PICSTRB : T2I_picst<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
|
|
} // isNotDuplicable = 1, AddedComplexity = 10
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Move Instructions.
|
|
//
|
|
|
|
let neverHasSideEffects = 1 in
|
|
def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
|
|
"mov", " $dst, $src", []>;
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
|
def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
|
|
"mov", " $dst, $src",
|
|
[(set GPR:$dst, t2_so_imm:$src)]>;
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
|
def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
|
|
"movw", " $dst, $src",
|
|
[(set GPR:$dst, imm0_65535:$src)]>;
|
|
|
|
// FIXME: Also available in ARM mode.
|
|
let Constraints = "$src = $dst" in
|
|
def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
|
|
"movt", " $dst, $imm",
|
|
[(set GPR:$dst,
|
|
(or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arithmetic Instructions.
|
|
//
|
|
|
|
defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
|
|
defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
|
|
|
|
// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
|
|
defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
|
|
defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
|
|
|
defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
|
|
defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
|
|
|
|
// RSB, RSC
|
|
defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
|
|
defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
|
defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
|
|
|
|
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
|
|
def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
|
|
(t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
|
|
def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
|
|
(t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Shift and rotate Instructions.
|
|
//
|
|
|
|
defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
|
|
defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
|
|
defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
|
|
defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
|
|
|
|
def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
|
|
"mov", " $dst, $src, rrx",
|
|
[(set GPR:$dst, (ARMrrx GPR:$src))]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Bitwise Instructions.
|
|
//
|
|
|
|
defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
|
|
defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
|
|
defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
|
|
|
|
defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
|
|
|
|
def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
|
|
(t2BICri GPR:$src, t2_so_imm_not:$imm)>;
|
|
|
|
defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
|
|
|
|
def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
|
|
(t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
|
|
|
|
// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
|
|
let AddedComplexity = 1 in
|
|
defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
|
|
|
|
def : T2Pat<(t2_so_imm_not:$src),
|
|
(t2MVNi t2_so_imm_not:$src)>;
|
|
|
|
// A8.6.17 BFC - Bitfield clear
|
|
// FIXME: Also available in ARM mode.
|
|
let Constraints = "$src = $dst" in
|
|
def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
|
|
"bfc", " $dst, $imm",
|
|
[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
|
|
|
|
// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Multiply Instructions.
|
|
//
|
|
let isCommutable = 1 in
|
|
def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|
"mul", " $dst, $a, $b",
|
|
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
|
|
|
|
def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|
"mla", " $dst, $a, $b, $c",
|
|
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
|
|
|
|
def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|
"mls", " $dst, $a, $b, $c",
|
|
[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
|
|
|
|
// FIXME: SMULL, etc.
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Misc. Arithmetic Instructions.
|
|
//
|
|
|
|
def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
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"clz", " $dst, $src",
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[(set GPR:$dst, (ctlz GPR:$src))]>;
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|
|
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def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
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|
"rev", " $dst, $src",
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[(set GPR:$dst, (bswap GPR:$src))]>;
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|
|
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def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
|
|
"rev16", " $dst, $src",
|
|
[(set GPR:$dst,
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|
(or (and (srl GPR:$src, (i32 8)), 0xFF),
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|
(or (and (shl GPR:$src, (i32 8)), 0xFF00),
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|
(or (and (srl GPR:$src, (i32 8)), 0xFF0000),
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|
(and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
|
|
|
|
/////
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|
/// A8.6.137 REVSH
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|
/////
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|
def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
|
|
"revsh", " $dst, $src",
|
|
[(set GPR:$dst,
|
|
(sext_inreg
|
|
(or (srl (and GPR:$src, 0xFFFF), (i32 8)),
|
|
(shl GPR:$src, (i32 8))), i16))]>;
|
|
|
|
// FIXME: PKHxx etc.
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Comparison Instructions...
|
|
//
|
|
|
|
defm t2CMP : T2I_cmp_is<"cmp",
|
|
BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
|
|
defm t2CMPz : T2I_cmp_is<"cmp",
|
|
BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
|
|
|
|
defm t2CMN : T2I_cmp_is<"cmn",
|
|
BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
|
|
defm t2CMNz : T2I_cmp_is<"cmn",
|
|
BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
|
|
|
|
def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
|
|
(t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
|
|
|
|
def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
|
|
(t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
|
|
|
|
defm t2TST : T2I_cmp_is<"tst",
|
|
BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
|
|
defm t2TEQ : T2I_cmp_is<"teq",
|
|
BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
|
|
|
|
// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
|
|
// Short range conditional branch. Looks awesome for loops. Need to figure
|
|
// out how to use this one.
|
|
|
|
// FIXME: Conditional moves
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Control-Flow Instructions
|
|
//
|
|
|
|
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
|
|
let isPredicable = 1 in
|
|
def t2B : T2XI<(outs), (ins brtarget:$target),
|
|
"b $target",
|
|
[(br bb:$target)]>;
|
|
|
|
let isNotDuplicable = 1, isIndirectBranch = 1 in {
|
|
def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
|
|
"mov pc, $target \n$jt",
|
|
[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
|
|
|
|
def t2BR_JTm :
|
|
T2JTI<(outs),
|
|
(ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id),
|
|
"ldr pc, $target \n$jt",
|
|
[(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt,
|
|
imm:$id)]>;
|
|
|
|
def t2BR_JTadd :
|
|
T2JTI<(outs),
|
|
(ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
|
|
"add pc, $target, $idx \n$jt",
|
|
[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>;
|
|
} // isNotDuplicate, isIndirectBranch
|
|
} // isBranch, isTerminator, isBarrier
|
|
|
|
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
|
|
// a two-value operand where a dag node expects two operands. :(
|
|
let isBranch = 1, isTerminator = 1 in
|
|
def t2Bcc : T2I<(outs), (ins brtarget:$target),
|
|
"b", " $target",
|
|
[/*(ARMbrcond bb:$target, imm:$cc)*/]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//
|
|
|
|
// ConstantPool, GlobalAddress, and JumpTable
|
|
def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
|
|
def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
|
|
def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
|
|
(t2LEApcrelJT tjumptable:$dst, imm:$id)>;
|
|
|
|
// Large immediate handling.
|
|
|
|
def : T2Pat<(i32 imm:$src),
|
|
(t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;
|