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https://github.com/c64scene-ar/llvm-6502.git
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6b7b725179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207505 91177308-0d34-0410-b5e6-96231b3b80d8
267 lines
7.4 KiB
C++
267 lines
7.4 KiB
C++
//===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that NVPTX uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef NVPTXISELLOWERING_H
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#define NVPTXISELLOWERING_H
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#include "NVPTX.h"
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#include "NVPTXSubtarget.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace NVPTXISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Wrapper,
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CALL,
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RET_FLAG,
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LOAD_PARAM,
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DeclareParam,
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DeclareScalarParam,
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DeclareRetParam,
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DeclareRet,
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DeclareScalarRet,
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PrintCall,
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PrintCallUni,
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CallArgBegin,
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CallArg,
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LastCallArg,
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CallArgEnd,
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CallVoid,
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CallVal,
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CallSymbol,
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Prototype,
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MoveParam,
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PseudoUseParam,
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RETURN,
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CallSeqBegin,
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CallSeqEnd,
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CallPrototype,
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Dummy,
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LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LoadV4,
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LDGV2, // LDG.v2
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LDGV4, // LDG.v4
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LDUV2, // LDU.v2
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LDUV4, // LDU.v4
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StoreV2,
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StoreV4,
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LoadParam,
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LoadParamV2,
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LoadParamV4,
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StoreParam,
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StoreParamV2,
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StoreParamV4,
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StoreParamS32, // to sext and store a <32bit value, not used currently
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StoreParamU32, // to zext and store a <32bit value, not used currently
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StoreRetval,
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StoreRetvalV2,
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StoreRetvalV4,
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// Texture intrinsics
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Tex1DFloatI32,
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Tex1DFloatFloat,
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Tex1DFloatFloatLevel,
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Tex1DFloatFloatGrad,
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Tex1DI32I32,
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Tex1DI32Float,
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Tex1DI32FloatLevel,
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Tex1DI32FloatGrad,
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Tex1DArrayFloatI32,
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Tex1DArrayFloatFloat,
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Tex1DArrayFloatFloatLevel,
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Tex1DArrayFloatFloatGrad,
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Tex1DArrayI32I32,
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Tex1DArrayI32Float,
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Tex1DArrayI32FloatLevel,
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Tex1DArrayI32FloatGrad,
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Tex2DFloatI32,
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Tex2DFloatFloat,
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Tex2DFloatFloatLevel,
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Tex2DFloatFloatGrad,
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Tex2DI32I32,
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Tex2DI32Float,
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Tex2DI32FloatLevel,
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Tex2DI32FloatGrad,
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Tex2DArrayFloatI32,
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Tex2DArrayFloatFloat,
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Tex2DArrayFloatFloatLevel,
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Tex2DArrayFloatFloatGrad,
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Tex2DArrayI32I32,
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Tex2DArrayI32Float,
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Tex2DArrayI32FloatLevel,
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Tex2DArrayI32FloatGrad,
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Tex3DFloatI32,
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Tex3DFloatFloat,
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Tex3DFloatFloatLevel,
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Tex3DFloatFloatGrad,
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Tex3DI32I32,
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Tex3DI32Float,
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Tex3DI32FloatLevel,
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Tex3DI32FloatGrad,
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// Surface intrinsics
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Suld1DI8Trap,
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Suld1DI16Trap,
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Suld1DI32Trap,
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Suld1DV2I8Trap,
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Suld1DV2I16Trap,
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Suld1DV2I32Trap,
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Suld1DV4I8Trap,
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Suld1DV4I16Trap,
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Suld1DV4I32Trap,
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Suld1DArrayI8Trap,
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Suld1DArrayI16Trap,
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Suld1DArrayI32Trap,
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Suld1DArrayV2I8Trap,
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Suld1DArrayV2I16Trap,
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Suld1DArrayV2I32Trap,
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Suld1DArrayV4I8Trap,
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Suld1DArrayV4I16Trap,
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Suld1DArrayV4I32Trap,
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Suld2DI8Trap,
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Suld2DI16Trap,
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Suld2DI32Trap,
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Suld2DV2I8Trap,
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Suld2DV2I16Trap,
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Suld2DV2I32Trap,
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Suld2DV4I8Trap,
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Suld2DV4I16Trap,
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Suld2DV4I32Trap,
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Suld2DArrayI8Trap,
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Suld2DArrayI16Trap,
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Suld2DArrayI32Trap,
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Suld2DArrayV2I8Trap,
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Suld2DArrayV2I16Trap,
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Suld2DArrayV2I32Trap,
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Suld2DArrayV4I8Trap,
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Suld2DArrayV4I16Trap,
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Suld2DArrayV4I32Trap,
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Suld3DI8Trap,
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Suld3DI16Trap,
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Suld3DI32Trap,
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Suld3DV2I8Trap,
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Suld3DV2I16Trap,
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Suld3DV2I32Trap,
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Suld3DV4I8Trap,
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Suld3DV4I16Trap,
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Suld3DV4I32Trap
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class NVPTXTargetLowering : public TargetLowering {
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public:
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explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
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SelectionDAG &DAG) const;
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const char *getTargetNodeName(unsigned Opcode) const override;
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bool isTypeSupportedInIntrinsic(MVT VT) const;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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unsigned Intrinsic) const override;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type
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/// Used to guide target specific optimizations, like loop strength
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/// reduction (LoopStrengthReduce.cpp) and memory optimization for
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/// address mode (CodeGenPrepare.cpp)
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bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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unsigned getFunctionAlignment(const Function *F) const;
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EVT getSetCCResultType(LLVMContext &, EVT VT) const override {
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if (VT.isVector())
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return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
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return MVT::i1;
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}
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ConstraintType
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getConstraintType(const std::string &Constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const override;
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SDValue LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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std::string getPrototype(Type *, const ArgListTy &,
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const SmallVectorImpl<ISD::OutputArg> &,
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unsigned retAlignment,
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const ImmutableCallSite *CS) const;
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SDValue
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LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
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SelectionDAG &DAG) const override;
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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NVPTXTargetMachine *nvTM;
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// PTX always uses 32-bit shift amounts
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MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
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bool shouldSplitVectorType(EVT VT) const override;
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private:
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const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
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SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx,
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EVT = MVT::i32) const;
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SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
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SDValue getParamHelpSymbol(SelectionDAG &DAG, int idx);
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
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Type *Ty, unsigned Idx) const;
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};
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} // namespace llvm
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#endif // NVPTXISELLOWERING_H
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