mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e2954c84e9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4502 91177308-0d34-0410-b5e6-96231b3b80d8
323 lines
11 KiB
C++
323 lines
11 KiB
C++
//===-- InstSelectSimple.cpp - A simple instruction selector for x86 ------===//
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//
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// This file defines a simple peephole instruction selector for the x86 platform
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iOther.h"
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#include "llvm/iPHINode.h"
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#include "llvm/Type.h"
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#include "llvm/Constants.h"
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#include "llvm/Pass.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/InstVisitor.h"
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#include <map>
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namespace {
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struct ISel : public FunctionPass, InstVisitor<ISel> {
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TargetMachine &TM;
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MachineFunction *F; // The function we are compiling into
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MachineBasicBlock *BB; // The current MBB we are compiling
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unsigned CurReg;
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std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
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ISel(TargetMachine &tm)
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: TM(tm), F(0), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
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/// runOnFunction - Top level implementation of instruction selection for
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/// the entire function.
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///
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bool runOnFunction(Function &Fn) {
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F = &MachineFunction::construct(&Fn, TM);
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visit(Fn);
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RegMap.clear();
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F = 0;
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return false; // We never modify the LLVM itself.
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}
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/// visitBasicBlock - This method is called when we are visiting a new basic
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/// block. This simply creates a new MachineBasicBlock to emit code into
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/// and adds it to the current MachineFunction. Subsequent visit* for
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/// instructions will be invoked for all instructions in the basic block.
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///
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void visitBasicBlock(BasicBlock &LLVM_BB) {
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BB = new MachineBasicBlock(&LLVM_BB);
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// FIXME: Use the auto-insert form when it's available
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F->getBasicBlockList().push_back(BB);
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}
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// Visitation methods for various instructions. These methods simply emit
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// fixed X86 code for each instruction.
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//
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void visitReturnInst(ReturnInst &RI);
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void visitBranchInst(BranchInst &BI);
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// Arithmetic operators
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void visitAdd(BinaryOperator &B);
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// Bitwise operators
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void visitAnd(BinaryOperator &B) { visitBitwise(B, 0); }
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void visitOr (BinaryOperator &B) { visitBitwise(B, 1); }
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void visitXor(BinaryOperator &B) { visitBitwise(B, 2); }
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void visitBitwise(BinaryOperator &B, unsigned OpcodeClass);
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// Binary comparison operators
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// Other operators
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void visitShiftInst(ShiftInst &I);
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void visitPHINode(PHINode &I);
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void visitInstruction(Instruction &I) {
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std::cerr << "Cannot instruction select: " << I;
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abort();
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void copyConstantToRegister(Constant *C, unsigned Reg);
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/// getReg - This method turns an LLVM value into a register number. This
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/// is guaranteed to produce the same register number for a particular value
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/// every time it is queried.
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///
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unsigned getReg(Value &V) { return getReg(&V); } // Allow references
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unsigned getReg(Value *V) {
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unsigned &Reg = RegMap[V];
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if (Reg == 0)
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Reg = CurReg++;
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// If this operand is a constant, emit the code to copy the constant into
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// the register here...
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//
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if (Constant *C = dyn_cast<Constant>(V))
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copyConstantToRegister(C, Reg);
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return Reg;
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}
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};
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}
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/// getClass - Turn a primitive type into a "class" number which is based on the
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/// size of the type, and whether or not it is floating point.
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///
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static inline unsigned getClass(const Type *Ty) {
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switch (Ty->getPrimitiveID()) {
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case Type::SByteTyID:
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case Type::UByteTyID: return 0; // Byte operands are class #0
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case Type::ShortTyID:
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case Type::UShortTyID: return 1; // Short operands are class #1
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return 2; // Int's and pointers are class #2
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case Type::LongTyID:
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case Type::ULongTyID: return 3; // Longs are class #3
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case Type::FloatTyID: return 4; // Float is class #4
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case Type::DoubleTyID: return 5; // Doubles are class #5
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default:
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assert(0 && "Invalid type to getClass!");
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return 0; // not reached
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}
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}
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/// copyConstantToRegister - Output the instructions required to put the
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/// specified constant into the specified register.
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///
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void ISel::copyConstantToRegister(Constant *C, unsigned R) {
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assert (!isa<ConstantExpr>(C) && "Constant expressions not yet handled!\n");
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if (C->getType()->isIntegral()) {
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unsigned Class = getClass(C->getType());
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assert(Class != 3 && "Type not handled yet!");
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static const unsigned IntegralOpcodeTab[] = {
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X86::MOVir8, X86::MOVir16, X86::MOVir32
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};
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if (C->getType()->isSigned()) {
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ConstantSInt *CSI = cast<ConstantSInt>(C);
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BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addSImm(CSI->getValue());
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} else {
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ConstantUInt *CUI = cast<ConstantUInt>(C);
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BuildMI(BB, IntegralOpcodeTab[Class], 1, R).addZImm(CUI->getValue());
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}
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} else {
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assert(0 && "Type not handled yet!");
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}
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}
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/// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
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/// we have the following possibilities:
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///
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/// ret void: No return value, simply emit a 'ret' instruction
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/// ret sbyte, ubyte : Extend value into EAX and return
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/// ret short, ushort: Extend value into EAX and return
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/// ret int, uint : Move value into EAX and return
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/// ret pointer : Move value into EAX and return
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/// ret long, ulong : Move value into EAX/EDX (?) and return
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/// ret float/double : ? Top of FP stack? XMM0?
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///
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void ISel::visitReturnInst(ReturnInst &I) {
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if (I.getNumOperands() != 0) { // Not 'ret void'?
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// Move result into a hard register... then emit a ret
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visitInstruction(I); // abort
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}
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// Emit a simple 'ret' instruction... appending it to the end of the basic
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// block
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BuildMI(BB, X86::RET, 0);
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}
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/// visitBranchInst - Handle conditional and unconditional branches here. Note
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/// that since code layout is frozen at this point, that if we are trying to
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/// jump to a block that is the immediate successor of the current block, we can
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/// just make a fall-through. (but we don't currently).
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///
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void ISel::visitBranchInst(BranchInst &BI) {
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if (BI.isConditional()) // Only handles unconditional branches so far...
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visitInstruction(BI);
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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}
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/// 'add' instruction - Simply turn this into an x86 reg,reg add instruction.
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void ISel::visitAdd(BinaryOperator &B) {
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unsigned Op0r = getReg(B.getOperand(0)), Op1r = getReg(B.getOperand(1));
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unsigned DestReg = getReg(B);
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unsigned Class = getClass(B.getType());
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static const unsigned Opcodes[] = { X86::ADDrr8, X86::ADDrr16, X86::ADDrr32 };
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if (Class >= sizeof(Opcodes)/sizeof(Opcodes[0]))
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visitInstruction(B); // Not handled class yet...
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BuildMI(BB, Opcodes[Class], 2, DestReg).addReg(Op0r).addReg(Op1r);
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// For Longs: Here we have a pair of operands each occupying a pair of
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// registers. We need to do an ADDrr32 of the least-significant pair
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// immediately followed by an ADCrr32 (Add with Carry) of the most-significant
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// pair. I don't know how we are representing these multi-register arguments.
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}
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/// visitBitwise - Implement the three bitwise operators for integral types...
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/// OperatorClass is one of: 0 for And, 1 for Or, 2 for Xor.
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void ISel::visitBitwise(BinaryOperator &B, unsigned OperatorClass) {
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if (B.getType() == Type::BoolTy) // FIXME: Handle bools
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visitInstruction(B);
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unsigned Class = getClass(B.getType());
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if (Class > 2) // FIXME: Handle longs
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visitInstruction(B);
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static const unsigned OpcodeTab[][4] = {
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{ X86::ANDrr8, X86::ANDrr16, X86::ANDrr32, 0 }, // AND
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{ X86:: ORrr8, X86:: ORrr16, X86:: ORrr32, 0 }, // OR
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{ X86::XORrr8, X86::XORrr16, X86::XORrr32, 0 }, // XOR
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};
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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unsigned Op0r = getReg(B.getOperand(0));
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unsigned Op1r = getReg(B.getOperand(1));
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BuildMI(BB, Opcode, 2, getReg(B)).addReg(Op0r).addReg(Op1r);
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}
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/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
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/// for constant immediate shift values, and for constant immediate
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/// shift values equal to 1. Even the general case is sort of special,
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/// because the shift amount has to be in CL, not just any old register.
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///
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void
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ISel::visitShiftInst (ShiftInst & I)
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{
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unsigned Op0r = getReg (I.getOperand (0));
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unsigned DestReg = getReg (I);
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bool isLeftShift = I.getOpcode() == Instruction::Shl;
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bool isOperandSigned = I.getType()->isUnsigned();
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unsigned OperandClass = getClass(I.getType());
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if (OperandClass > 2)
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visitInstruction(I); // Can't handle longs yet!
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if (ConstantUInt *CUI = dyn_cast <ConstantUInt> (I.getOperand (1)))
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{
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// The shift amount is constant, guaranteed to be a ubyte. Get its value.
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assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
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unsigned char shAmt = CUI->getValue();
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static const unsigned ConstantOperand[][4] = {
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{ X86::SHRir8, X86::SHRir16, X86::SHRir32, 0 }, // SHR
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{ X86::SARir8, X86::SARir16, X86::SARir32, 0 }, // SAR
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{ X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SHL
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{ X86::SHLir8, X86::SHLir16, X86::SHLir32, 0 }, // SAL = SHL
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};
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const unsigned *OpTab = // Figure out the operand table to use
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ConstantOperand[isLeftShift*2+isOperandSigned];
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// Emit: <insn> reg, shamt (shift-by-immediate opcode "ir" form.)
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BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addZImm(shAmt);
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}
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else
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{
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// The shift amount is non-constant.
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//
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// In fact, you can only shift with a variable shift amount if
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// that amount is already in the CL register, so we have to put it
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// there first.
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//
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// Emit: move cl, shiftAmount (put the shift amount in CL.)
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BuildMI (BB, X86::MOVrr8, 2, X86::CL).addReg(getReg(I.getOperand(1)));
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// This is a shift right (SHR).
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static const unsigned NonConstantOperand[][4] = {
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{ X86::SHRrr8, X86::SHRrr16, X86::SHRrr32, 0 }, // SHR
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{ X86::SARrr8, X86::SARrr16, X86::SARrr32, 0 }, // SAR
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{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SHL
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{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32, 0 }, // SAL = SHL
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};
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const unsigned *OpTab = // Figure out the operand table to use
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NonConstantOperand[isLeftShift*2+isOperandSigned];
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BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
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}
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}
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/// visitPHINode - Turn an LLVM PHI node into an X86 PHI node...
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///
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void ISel::visitPHINode(PHINode &PN) {
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MachineInstr *MI = BuildMI(BB, X86::PHI, PN.getNumOperands(), getReg(PN));
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for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
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// FIXME: This will put constants after the PHI nodes in the block, which
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// is invalid. They should be put inline into the PHI node eventually.
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//
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MI->addRegOperand(getReg(PN.getIncomingValue(i)));
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MI->addPCDispOperand(PN.getIncomingBlock(i));
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}
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}
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/// createSimpleX86InstructionSelector - This pass converts an LLVM function
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/// into a machine code representation is a very simple peep-hole fashion. The
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/// generated code sucks but the implementation is nice and simple.
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///
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Pass *createSimpleX86InstructionSelector(TargetMachine &TM) {
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return new ISel(TM);
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}
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