Jack Carter e2a9376b1b [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) ... Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-15 12:24:57 +00:00
..
AArch64	Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions	2013-08-15 08:26:11 +00:00
ARM	Let t2LDRBi8 and t2LDRBi12 have same Base Pointer	2013-08-14 16:35:29 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)	2013-08-15 12:24:57 +00:00
MSP430
NVPTX	[NVPTX] Add missing patterns for i1 [s,u]int_to_fp	2013-08-06 14:13:34 +00:00
PowerPC	Actually fix PPC64 64-bit GPR inline asm constraint matching	2013-08-14 20:05:04 +00:00
R600	R600/SI: Improve legalization of vector operations	2013-08-14 23:25:00 +00:00
SI
SPARC
SystemZ	[SystemZ] Use CLC and IPM to implement memcmp	2013-08-12 10:28:10 +00:00
Thumb
Thumb2
X86	Revert r188449 as it turns out we're just missing the instructions that need the v16i32/v16f32 matching.	2013-08-15 08:38:25 +00:00
XCore