Tom Stellard 38aad1c16a R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips ...

The src and dst register cannot be the same on chips with 16 lds banks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238147 91177308-0d34-0410-b5e6-96231b3b80d8

2015-05-25 16:15:54 +00:00

..

Analysis

Revert r236894 "[BasicAA] Fix zext & sext handling"

2015-05-22 01:27:37 +00:00

Assembler

IR / debug info: Add a DWOId field to DICompileUnit,

2015-05-21 20:37:30 +00:00

Bindings

…

Bitcode

IR / debug info: Add a DWOId field to DICompileUnit,

2015-05-21 20:37:30 +00:00

BugPoint

…

CodeGen

R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips

2015-05-25 16:15:54 +00:00

DebugInfo

AsmPrinter: Emit the DwarfStringPool offset directly when possible

2015-05-24 16:14:59 +00:00

ExecutionEngine

…

Feature

…

FileCheck

…

Instrumentation

…

Integer

…

JitListener

…

Linker

…

LTO

…

MC

This patch adds support for the vector quadword add/sub instructions introduced

2015-05-25 15:49:26 +00:00

Object

Stop inventing symbol sizes.

2015-05-22 15:43:00 +00:00

Other

…

SymbolRewriter

…

TableGen

[TableGen] Resolve complex def names inside multiclasses

2015-05-21 04:32:56 +00:00

tools

Stop inventing symbol sizes.

2015-05-22 15:43:00 +00:00

Transforms

Correct a mistaken comment from 238071 [NFC]

2015-05-23 00:05:43 +00:00

Unit

…

Verifier

…

YAMLParser

…

.clang-format

…

CMakeLists.txt

…

lit.cfg

…

lit.site.cfg.in

…

Makefile

…

Makefile.tests

…

TestRunner.sh

…