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https://github.com/c64scene-ar/llvm-6502.git
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015f228861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
328 lines
10 KiB
C++
328 lines
10 KiB
C++
//===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the XCore implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreRegisterInfo.h"
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#include "XCoreMachineFunctionInfo.h"
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#include "XCore.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Type.h"
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#include "llvm/Function.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#define GET_REGINFO_TARGET_DESC
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#include "XCoreGenRegisterInfo.inc"
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using namespace llvm;
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XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
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: XCoreGenRegisterInfo(XCore::LR), TII(tii) {
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}
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// helper functions
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static inline bool isImmUs(unsigned val) {
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return val <= 11;
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}
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static inline bool isImmU6(unsigned val) {
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return val < (1 << 6);
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}
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static inline bool isImmU16(unsigned val) {
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return val < (1 << 16);
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}
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static const unsigned XCore_ArgRegs[] = {
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XCore::R0, XCore::R1, XCore::R2, XCore::R3
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};
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const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
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{
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return XCore_ArgRegs;
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}
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unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
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{
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return array_lengthof(XCore_ArgRegs);
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}
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bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
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return MF.getMMI().hasDebugInfo() ||
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MF.getFunction()->needsUnwindTableEntry();
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}
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const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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static const uint16_t CalleeSavedRegs[] = {
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XCore::R4, XCore::R5, XCore::R6, XCore::R7,
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XCore::R8, XCore::R9, XCore::R10, XCore::LR,
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0
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};
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return CalleeSavedRegs;
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}
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BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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Reserved.set(XCore::CP);
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Reserved.set(XCore::DP);
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Reserved.set(XCore::SP);
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Reserved.set(XCore::LR);
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if (TFI->hasFP(MF)) {
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Reserved.set(XCore::R10);
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}
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return Reserved;
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}
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bool
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XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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// TODO can we estimate stack size?
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return TFI->hasFP(MF);
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}
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bool
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XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
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return false;
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}
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// This function eliminates ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void XCoreRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (!TFI->hasReservedCallFrame(MF)) {
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// Turn the adjcallstackdown instruction into 'extsp <amt>' and the
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// adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
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MachineInstr *Old = I;
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uint64_t Amount = Old->getOperand(0).getImm();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = TFI->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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assert(Amount%4 == 0);
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Amount /= 4;
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bool isU6 = isImmU6(Amount);
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if (!isU6 && !isImmU16(Amount)) {
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// FIX could emit multiple instructions in this case.
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#ifndef NDEBUG
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errs() << "eliminateCallFramePseudoInstr size too big: "
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<< Amount << "\n";
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#endif
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llvm_unreachable(0);
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}
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MachineInstr *New;
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if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
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int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
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New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
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.addImm(Amount);
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} else {
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assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
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int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
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New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
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.addImm(Amount);
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}
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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void
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XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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DebugLoc dl = MI.getDebugLoc();
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unsigned i = 0;
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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MachineOperand &FrameOp = MI.getOperand(i);
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int FrameIndex = FrameOp.getIndex();
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MachineFunction &MF = *MI.getParent()->getParent();
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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int StackSize = MF.getFrameInfo()->getStackSize();
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#ifndef NDEBUG
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DEBUG(errs() << "\nFunction : "
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<< MF.getFunction()->getName() << "\n");
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DEBUG(errs() << "<--------->\n");
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DEBUG(MI.print(errs()));
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DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
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DEBUG(errs() << "FrameOffset : " << Offset << "\n");
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DEBUG(errs() << "StackSize : " << StackSize << "\n");
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#endif
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Offset += StackSize;
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unsigned FrameReg = getFrameRegister(MF);
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// Special handling of DBG_VALUE instructions.
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if (MI.isDebugValue()) {
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MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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return;
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}
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// fold constant into offset.
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Offset += MI.getOperand(i + 1).getImm();
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MI.getOperand(i + 1).ChangeToImmediate(0);
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assert(Offset%4 == 0 && "Misaligned stack offset");
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DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
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Offset/=4;
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bool FP = TFI->hasFP(MF);
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unsigned Reg = MI.getOperand(0).getReg();
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bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
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assert(XCore::GRRegsRegisterClass->contains(Reg) &&
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"Unexpected register operand");
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MachineBasicBlock &MBB = *MI.getParent();
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if (FP) {
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bool isUs = isImmUs(Offset);
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if (!isUs) {
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if (!RS)
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report_fatal_error("eliminateFrameIndex Frame size too big: " +
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Twine(Offset));
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unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
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SPAdj);
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loadConstant(MBB, II, ScratchReg, Offset, dl);
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switch (MI.getOpcode()) {
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case XCore::LDWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
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.addReg(FrameReg)
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.addReg(ScratchReg, RegState::Kill);
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break;
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case XCore::STWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
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.addReg(Reg, getKillRegState(isKill))
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.addReg(FrameReg)
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.addReg(ScratchReg, RegState::Kill);
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break;
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case XCore::LDAWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
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.addReg(FrameReg)
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.addReg(ScratchReg, RegState::Kill);
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break;
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default:
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llvm_unreachable("Unexpected Opcode");
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}
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} else {
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switch (MI.getOpcode()) {
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case XCore::LDWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
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.addReg(FrameReg)
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.addImm(Offset);
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break;
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case XCore::STWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
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.addReg(Reg, getKillRegState(isKill))
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.addReg(FrameReg)
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.addImm(Offset);
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break;
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case XCore::LDAWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
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.addReg(FrameReg)
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.addImm(Offset);
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break;
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default:
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llvm_unreachable("Unexpected Opcode");
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}
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}
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} else {
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bool isU6 = isImmU6(Offset);
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if (!isU6 && !isImmU16(Offset))
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report_fatal_error("eliminateFrameIndex Frame size too big: " +
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Twine(Offset));
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switch (MI.getOpcode()) {
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int NewOpcode;
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case XCore::LDWFI:
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NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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.addImm(Offset);
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break;
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case XCore::STWFI:
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NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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BuildMI(MBB, II, dl, TII.get(NewOpcode))
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.addReg(Reg, getKillRegState(isKill))
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.addImm(Offset);
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break;
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case XCore::LDAWFI:
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NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
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BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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.addImm(Offset);
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break;
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default:
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llvm_unreachable("Unexpected Opcode");
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}
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}
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// Erase old instruction.
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MBB.erase(II);
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}
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void XCoreRegisterInfo::
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loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DstReg, int64_t Value, DebugLoc dl) const {
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// TODO use mkmsk if possible.
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if (!isImmU16(Value)) {
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// TODO use constant pool.
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report_fatal_error("loadConstant value too big " + Twine(Value));
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}
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int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
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BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
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}
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unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
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}
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