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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227159 91177308-0d34-0410-b5e6-96231b3b80d8
550 lines
20 KiB
C++
550 lines
20 KiB
C++
//===-- AtomicExpandPass.cpp - Expand atomic instructions -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass (at IR level) to replace atomic instructions with
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// either (intrinsic-based) load-linked/store-conditional loops or AtomicCmpXchg.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstIterator.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "atomic-expand"
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namespace {
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class AtomicExpand: public FunctionPass {
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const TargetMachine *TM;
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const TargetLowering *TLI;
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public:
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static char ID; // Pass identification, replacement for typeid
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explicit AtomicExpand(const TargetMachine *TM = nullptr)
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: FunctionPass(ID), TM(TM), TLI(nullptr) {
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initializeAtomicExpandPass(*PassRegistry::getPassRegistry());
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}
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bool runOnFunction(Function &F) override;
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private:
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bool bracketInstWithFences(Instruction *I, AtomicOrdering Order,
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bool IsStore, bool IsLoad);
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bool expandAtomicLoad(LoadInst *LI);
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bool expandAtomicLoadToLL(LoadInst *LI);
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bool expandAtomicLoadToCmpXchg(LoadInst *LI);
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bool expandAtomicStore(StoreInst *SI);
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bool expandAtomicRMW(AtomicRMWInst *AI);
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bool expandAtomicRMWToLLSC(AtomicRMWInst *AI);
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bool expandAtomicRMWToCmpXchg(AtomicRMWInst *AI);
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bool expandAtomicCmpXchg(AtomicCmpXchgInst *CI);
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bool isIdempotentRMW(AtomicRMWInst *AI);
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bool simplifyIdempotentRMW(AtomicRMWInst *AI);
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};
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}
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char AtomicExpand::ID = 0;
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char &llvm::AtomicExpandID = AtomicExpand::ID;
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INITIALIZE_TM_PASS(AtomicExpand, "atomic-expand",
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"Expand Atomic calls in terms of either load-linked & store-conditional or cmpxchg",
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false, false)
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FunctionPass *llvm::createAtomicExpandPass(const TargetMachine *TM) {
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return new AtomicExpand(TM);
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}
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bool AtomicExpand::runOnFunction(Function &F) {
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if (!TM || !TM->getSubtargetImpl(F)->enableAtomicExpand())
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return false;
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TLI = TM->getSubtargetImpl(F)->getTargetLowering();
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SmallVector<Instruction *, 1> AtomicInsts;
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// Changing control-flow while iterating through it is a bad idea, so gather a
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// list of all atomic instructions before we start.
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for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) {
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if (I->isAtomic())
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AtomicInsts.push_back(&*I);
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}
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bool MadeChange = false;
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for (auto I : AtomicInsts) {
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auto LI = dyn_cast<LoadInst>(I);
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auto SI = dyn_cast<StoreInst>(I);
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auto RMWI = dyn_cast<AtomicRMWInst>(I);
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auto CASI = dyn_cast<AtomicCmpXchgInst>(I);
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assert((LI || SI || RMWI || CASI || isa<FenceInst>(I)) &&
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"Unknown atomic instruction");
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auto FenceOrdering = Monotonic;
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bool IsStore, IsLoad;
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if (TLI->getInsertFencesForAtomic()) {
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if (LI && isAtLeastAcquire(LI->getOrdering())) {
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FenceOrdering = LI->getOrdering();
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LI->setOrdering(Monotonic);
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IsStore = false;
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IsLoad = true;
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} else if (SI && isAtLeastRelease(SI->getOrdering())) {
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FenceOrdering = SI->getOrdering();
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SI->setOrdering(Monotonic);
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IsStore = true;
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IsLoad = false;
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} else if (RMWI && (isAtLeastRelease(RMWI->getOrdering()) ||
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isAtLeastAcquire(RMWI->getOrdering()))) {
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FenceOrdering = RMWI->getOrdering();
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RMWI->setOrdering(Monotonic);
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IsStore = IsLoad = true;
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} else if (CASI && !TLI->hasLoadLinkedStoreConditional() &&
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(isAtLeastRelease(CASI->getSuccessOrdering()) ||
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isAtLeastAcquire(CASI->getSuccessOrdering()))) {
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// If a compare and swap is lowered to LL/SC, we can do smarter fence
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// insertion, with a stronger one on the success path than on the
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// failure path. As a result, fence insertion is directly done by
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// expandAtomicCmpXchg in that case.
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FenceOrdering = CASI->getSuccessOrdering();
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CASI->setSuccessOrdering(Monotonic);
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CASI->setFailureOrdering(Monotonic);
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IsStore = IsLoad = true;
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}
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if (FenceOrdering != Monotonic) {
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MadeChange |= bracketInstWithFences(I, FenceOrdering, IsStore, IsLoad);
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}
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}
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if (LI && TLI->shouldExpandAtomicLoadInIR(LI)) {
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MadeChange |= expandAtomicLoad(LI);
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} else if (SI && TLI->shouldExpandAtomicStoreInIR(SI)) {
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MadeChange |= expandAtomicStore(SI);
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} else if (RMWI) {
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// There are two different ways of expanding RMW instructions:
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// - into a load if it is idempotent
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// - into a Cmpxchg/LL-SC loop otherwise
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// we try them in that order.
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MadeChange |=
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(isIdempotentRMW(RMWI) && simplifyIdempotentRMW(RMWI)) ||
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(TLI->shouldExpandAtomicRMWInIR(RMWI) && expandAtomicRMW(RMWI));
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} else if (CASI && TLI->hasLoadLinkedStoreConditional()) {
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MadeChange |= expandAtomicCmpXchg(CASI);
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}
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}
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return MadeChange;
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}
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bool AtomicExpand::bracketInstWithFences(Instruction *I, AtomicOrdering Order,
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bool IsStore, bool IsLoad) {
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IRBuilder<> Builder(I);
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auto LeadingFence = TLI->emitLeadingFence(Builder, Order, IsStore, IsLoad);
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auto TrailingFence = TLI->emitTrailingFence(Builder, Order, IsStore, IsLoad);
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// The trailing fence is emitted before the instruction instead of after
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// because there is no easy way of setting Builder insertion point after
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// an instruction. So we must erase it from the BB, and insert it back
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// in the right place.
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// We have a guard here because not every atomic operation generates a
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// trailing fence.
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if (TrailingFence) {
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TrailingFence->removeFromParent();
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TrailingFence->insertAfter(I);
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}
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return (LeadingFence || TrailingFence);
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}
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bool AtomicExpand::expandAtomicLoad(LoadInst *LI) {
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if (TLI->hasLoadLinkedStoreConditional())
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return expandAtomicLoadToLL(LI);
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else
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return expandAtomicLoadToCmpXchg(LI);
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}
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bool AtomicExpand::expandAtomicLoadToLL(LoadInst *LI) {
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IRBuilder<> Builder(LI);
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// On some architectures, load-linked instructions are atomic for larger
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// sizes than normal loads. For example, the only 64-bit load guaranteed
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// to be single-copy atomic by ARM is an ldrexd (A3.5.3).
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Value *Val =
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TLI->emitLoadLinked(Builder, LI->getPointerOperand(), LI->getOrdering());
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LI->replaceAllUsesWith(Val);
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LI->eraseFromParent();
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return true;
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}
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bool AtomicExpand::expandAtomicLoadToCmpXchg(LoadInst *LI) {
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IRBuilder<> Builder(LI);
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AtomicOrdering Order = LI->getOrdering();
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Value *Addr = LI->getPointerOperand();
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Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
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Constant *DummyVal = Constant::getNullValue(Ty);
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Value *Pair = Builder.CreateAtomicCmpXchg(
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Addr, DummyVal, DummyVal, Order,
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AtomicCmpXchgInst::getStrongestFailureOrdering(Order));
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Value *Loaded = Builder.CreateExtractValue(Pair, 0, "loaded");
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LI->replaceAllUsesWith(Loaded);
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LI->eraseFromParent();
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return true;
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}
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bool AtomicExpand::expandAtomicStore(StoreInst *SI) {
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// This function is only called on atomic stores that are too large to be
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// atomic if implemented as a native store. So we replace them by an
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// atomic swap, that can be implemented for example as a ldrex/strex on ARM
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// or lock cmpxchg8/16b on X86, as these are atomic for larger sizes.
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// It is the responsibility of the target to only return true in
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// shouldExpandAtomicRMW in cases where this is required and possible.
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IRBuilder<> Builder(SI);
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AtomicRMWInst *AI =
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Builder.CreateAtomicRMW(AtomicRMWInst::Xchg, SI->getPointerOperand(),
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SI->getValueOperand(), SI->getOrdering());
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SI->eraseFromParent();
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// Now we have an appropriate swap instruction, lower it as usual.
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return expandAtomicRMW(AI);
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}
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bool AtomicExpand::expandAtomicRMW(AtomicRMWInst *AI) {
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if (TLI->hasLoadLinkedStoreConditional())
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return expandAtomicRMWToLLSC(AI);
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else
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return expandAtomicRMWToCmpXchg(AI);
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}
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/// Emit IR to implement the given atomicrmw operation on values in registers,
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/// returning the new value.
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static Value *performAtomicOp(AtomicRMWInst::BinOp Op, IRBuilder<> &Builder,
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Value *Loaded, Value *Inc) {
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Value *NewVal;
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switch (Op) {
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case AtomicRMWInst::Xchg:
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return Inc;
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case AtomicRMWInst::Add:
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return Builder.CreateAdd(Loaded, Inc, "new");
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case AtomicRMWInst::Sub:
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return Builder.CreateSub(Loaded, Inc, "new");
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case AtomicRMWInst::And:
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return Builder.CreateAnd(Loaded, Inc, "new");
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case AtomicRMWInst::Nand:
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return Builder.CreateNot(Builder.CreateAnd(Loaded, Inc), "new");
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case AtomicRMWInst::Or:
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return Builder.CreateOr(Loaded, Inc, "new");
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case AtomicRMWInst::Xor:
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return Builder.CreateXor(Loaded, Inc, "new");
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case AtomicRMWInst::Max:
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NewVal = Builder.CreateICmpSGT(Loaded, Inc);
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return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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case AtomicRMWInst::Min:
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NewVal = Builder.CreateICmpSLE(Loaded, Inc);
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return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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case AtomicRMWInst::UMax:
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NewVal = Builder.CreateICmpUGT(Loaded, Inc);
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return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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case AtomicRMWInst::UMin:
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NewVal = Builder.CreateICmpULE(Loaded, Inc);
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return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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default:
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llvm_unreachable("Unknown atomic op");
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}
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}
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bool AtomicExpand::expandAtomicRMWToLLSC(AtomicRMWInst *AI) {
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AtomicOrdering MemOpOrder = AI->getOrdering();
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Value *Addr = AI->getPointerOperand();
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BasicBlock *BB = AI->getParent();
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Function *F = BB->getParent();
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LLVMContext &Ctx = F->getContext();
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// Given: atomicrmw some_op iN* %addr, iN %incr ordering
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//
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// The standard expansion we produce is:
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// [...]
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// fence?
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// atomicrmw.start:
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// %loaded = @load.linked(%addr)
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// %new = some_op iN %loaded, %incr
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// %stored = @store_conditional(%new, %addr)
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// %try_again = icmp i32 ne %stored, 0
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// br i1 %try_again, label %loop, label %atomicrmw.end
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// atomicrmw.end:
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// fence?
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// [...]
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BasicBlock *ExitBB = BB->splitBasicBlock(AI, "atomicrmw.end");
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BasicBlock *LoopBB = BasicBlock::Create(Ctx, "atomicrmw.start", F, ExitBB);
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// This grabs the DebugLoc from AI.
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IRBuilder<> Builder(AI);
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// The split call above "helpfully" added a branch at the end of BB (to the
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// wrong place), but we might want a fence too. It's easiest to just remove
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// the branch entirely.
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std::prev(BB->end())->eraseFromParent();
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Builder.SetInsertPoint(BB);
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Builder.CreateBr(LoopBB);
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// Start the main loop block now that we've taken care of the preliminaries.
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Builder.SetInsertPoint(LoopBB);
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Value *Loaded = TLI->emitLoadLinked(Builder, Addr, MemOpOrder);
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Value *NewVal =
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performAtomicOp(AI->getOperation(), Builder, Loaded, AI->getValOperand());
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Value *StoreSuccess =
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TLI->emitStoreConditional(Builder, NewVal, Addr, MemOpOrder);
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Value *TryAgain = Builder.CreateICmpNE(
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StoreSuccess, ConstantInt::get(IntegerType::get(Ctx, 32), 0), "tryagain");
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Builder.CreateCondBr(TryAgain, LoopBB, ExitBB);
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Builder.SetInsertPoint(ExitBB, ExitBB->begin());
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AI->replaceAllUsesWith(Loaded);
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AI->eraseFromParent();
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return true;
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}
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bool AtomicExpand::expandAtomicRMWToCmpXchg(AtomicRMWInst *AI) {
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AtomicOrdering MemOpOrder =
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AI->getOrdering() == Unordered ? Monotonic : AI->getOrdering();
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Value *Addr = AI->getPointerOperand();
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BasicBlock *BB = AI->getParent();
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Function *F = BB->getParent();
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LLVMContext &Ctx = F->getContext();
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// Given: atomicrmw some_op iN* %addr, iN %incr ordering
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//
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// The standard expansion we produce is:
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// [...]
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// %init_loaded = load atomic iN* %addr
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// br label %loop
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// loop:
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// %loaded = phi iN [ %init_loaded, %entry ], [ %new_loaded, %loop ]
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// %new = some_op iN %loaded, %incr
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// %pair = cmpxchg iN* %addr, iN %loaded, iN %new
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// %new_loaded = extractvalue { iN, i1 } %pair, 0
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// %success = extractvalue { iN, i1 } %pair, 1
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// br i1 %success, label %atomicrmw.end, label %loop
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// atomicrmw.end:
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// [...]
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BasicBlock *ExitBB = BB->splitBasicBlock(AI, "atomicrmw.end");
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BasicBlock *LoopBB = BasicBlock::Create(Ctx, "atomicrmw.start", F, ExitBB);
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// This grabs the DebugLoc from AI.
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IRBuilder<> Builder(AI);
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// The split call above "helpfully" added a branch at the end of BB (to the
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// wrong place), but we want a load. It's easiest to just remove
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// the branch entirely.
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std::prev(BB->end())->eraseFromParent();
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Builder.SetInsertPoint(BB);
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LoadInst *InitLoaded = Builder.CreateLoad(Addr);
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// Atomics require at least natural alignment.
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InitLoaded->setAlignment(AI->getType()->getPrimitiveSizeInBits());
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Builder.CreateBr(LoopBB);
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// Start the main loop block now that we've taken care of the preliminaries.
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Builder.SetInsertPoint(LoopBB);
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PHINode *Loaded = Builder.CreatePHI(AI->getType(), 2, "loaded");
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Loaded->addIncoming(InitLoaded, BB);
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Value *NewVal =
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performAtomicOp(AI->getOperation(), Builder, Loaded, AI->getValOperand());
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Value *Pair = Builder.CreateAtomicCmpXchg(
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Addr, Loaded, NewVal, MemOpOrder,
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AtomicCmpXchgInst::getStrongestFailureOrdering(MemOpOrder));
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Value *NewLoaded = Builder.CreateExtractValue(Pair, 0, "newloaded");
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Loaded->addIncoming(NewLoaded, LoopBB);
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Value *Success = Builder.CreateExtractValue(Pair, 1, "success");
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Builder.CreateCondBr(Success, ExitBB, LoopBB);
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Builder.SetInsertPoint(ExitBB, ExitBB->begin());
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AI->replaceAllUsesWith(NewLoaded);
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AI->eraseFromParent();
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return true;
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}
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bool AtomicExpand::expandAtomicCmpXchg(AtomicCmpXchgInst *CI) {
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AtomicOrdering SuccessOrder = CI->getSuccessOrdering();
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AtomicOrdering FailureOrder = CI->getFailureOrdering();
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Value *Addr = CI->getPointerOperand();
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BasicBlock *BB = CI->getParent();
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Function *F = BB->getParent();
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LLVMContext &Ctx = F->getContext();
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// If getInsertFencesForAtomic() returns true, then the target does not want
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// to deal with memory orders, and emitLeading/TrailingFence should take care
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// of everything. Otherwise, emitLeading/TrailingFence are no-op and we
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// should preserve the ordering.
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AtomicOrdering MemOpOrder =
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TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder;
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// Given: cmpxchg some_op iN* %addr, iN %desired, iN %new success_ord fail_ord
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//
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// The full expansion we produce is:
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// [...]
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// fence?
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// cmpxchg.start:
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// %loaded = @load.linked(%addr)
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// %should_store = icmp eq %loaded, %desired
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// br i1 %should_store, label %cmpxchg.trystore,
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// label %cmpxchg.failure
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// cmpxchg.trystore:
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// %stored = @store_conditional(%new, %addr)
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// %success = icmp eq i32 %stored, 0
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// br i1 %success, label %cmpxchg.success, label %loop/%cmpxchg.failure
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// cmpxchg.success:
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// fence?
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// br label %cmpxchg.end
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// cmpxchg.failure:
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// fence?
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// br label %cmpxchg.end
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// cmpxchg.end:
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// %success = phi i1 [true, %cmpxchg.success], [false, %cmpxchg.failure]
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// %restmp = insertvalue { iN, i1 } undef, iN %loaded, 0
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// %res = insertvalue { iN, i1 } %restmp, i1 %success, 1
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// [...]
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BasicBlock *ExitBB = BB->splitBasicBlock(CI, "cmpxchg.end");
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auto FailureBB = BasicBlock::Create(Ctx, "cmpxchg.failure", F, ExitBB);
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auto SuccessBB = BasicBlock::Create(Ctx, "cmpxchg.success", F, FailureBB);
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auto TryStoreBB = BasicBlock::Create(Ctx, "cmpxchg.trystore", F, SuccessBB);
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auto LoopBB = BasicBlock::Create(Ctx, "cmpxchg.start", F, TryStoreBB);
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// This grabs the DebugLoc from CI
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IRBuilder<> Builder(CI);
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// The split call above "helpfully" added a branch at the end of BB (to the
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// wrong place), but we might want a fence too. It's easiest to just remove
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// the branch entirely.
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std::prev(BB->end())->eraseFromParent();
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Builder.SetInsertPoint(BB);
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TLI->emitLeadingFence(Builder, SuccessOrder, /*IsStore=*/true,
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/*IsLoad=*/true);
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Builder.CreateBr(LoopBB);
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// Start the main loop block now that we've taken care of the preliminaries.
|
|
Builder.SetInsertPoint(LoopBB);
|
|
Value *Loaded = TLI->emitLoadLinked(Builder, Addr, MemOpOrder);
|
|
Value *ShouldStore =
|
|
Builder.CreateICmpEQ(Loaded, CI->getCompareOperand(), "should_store");
|
|
|
|
// If the the cmpxchg doesn't actually need any ordering when it fails, we can
|
|
// jump straight past that fence instruction (if it exists).
|
|
Builder.CreateCondBr(ShouldStore, TryStoreBB, FailureBB);
|
|
|
|
Builder.SetInsertPoint(TryStoreBB);
|
|
Value *StoreSuccess = TLI->emitStoreConditional(
|
|
Builder, CI->getNewValOperand(), Addr, MemOpOrder);
|
|
StoreSuccess = Builder.CreateICmpEQ(
|
|
StoreSuccess, ConstantInt::get(Type::getInt32Ty(Ctx), 0), "success");
|
|
Builder.CreateCondBr(StoreSuccess, SuccessBB,
|
|
CI->isWeak() ? FailureBB : LoopBB);
|
|
|
|
// Make sure later instructions don't get reordered with a fence if necessary.
|
|
Builder.SetInsertPoint(SuccessBB);
|
|
TLI->emitTrailingFence(Builder, SuccessOrder, /*IsStore=*/true,
|
|
/*IsLoad=*/true);
|
|
Builder.CreateBr(ExitBB);
|
|
|
|
Builder.SetInsertPoint(FailureBB);
|
|
TLI->emitTrailingFence(Builder, FailureOrder, /*IsStore=*/true,
|
|
/*IsLoad=*/true);
|
|
Builder.CreateBr(ExitBB);
|
|
|
|
// Finally, we have control-flow based knowledge of whether the cmpxchg
|
|
// succeeded or not. We expose this to later passes by converting any
|
|
// subsequent "icmp eq/ne %loaded, %oldval" into a use of an appropriate PHI.
|
|
|
|
// Setup the builder so we can create any PHIs we need.
|
|
Builder.SetInsertPoint(ExitBB, ExitBB->begin());
|
|
PHINode *Success = Builder.CreatePHI(Type::getInt1Ty(Ctx), 2);
|
|
Success->addIncoming(ConstantInt::getTrue(Ctx), SuccessBB);
|
|
Success->addIncoming(ConstantInt::getFalse(Ctx), FailureBB);
|
|
|
|
// Look for any users of the cmpxchg that are just comparing the loaded value
|
|
// against the desired one, and replace them with the CFG-derived version.
|
|
SmallVector<ExtractValueInst *, 2> PrunedInsts;
|
|
for (auto User : CI->users()) {
|
|
ExtractValueInst *EV = dyn_cast<ExtractValueInst>(User);
|
|
if (!EV)
|
|
continue;
|
|
|
|
assert(EV->getNumIndices() == 1 && EV->getIndices()[0] <= 1 &&
|
|
"weird extraction from { iN, i1 }");
|
|
|
|
if (EV->getIndices()[0] == 0)
|
|
EV->replaceAllUsesWith(Loaded);
|
|
else
|
|
EV->replaceAllUsesWith(Success);
|
|
|
|
PrunedInsts.push_back(EV);
|
|
}
|
|
|
|
// We can remove the instructions now we're no longer iterating through them.
|
|
for (auto EV : PrunedInsts)
|
|
EV->eraseFromParent();
|
|
|
|
if (!CI->use_empty()) {
|
|
// Some use of the full struct return that we don't understand has happened,
|
|
// so we've got to reconstruct it properly.
|
|
Value *Res;
|
|
Res = Builder.CreateInsertValue(UndefValue::get(CI->getType()), Loaded, 0);
|
|
Res = Builder.CreateInsertValue(Res, Success, 1);
|
|
|
|
CI->replaceAllUsesWith(Res);
|
|
}
|
|
|
|
CI->eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
bool AtomicExpand::isIdempotentRMW(AtomicRMWInst* RMWI) {
|
|
auto C = dyn_cast<ConstantInt>(RMWI->getValOperand());
|
|
if(!C)
|
|
return false;
|
|
|
|
AtomicRMWInst::BinOp Op = RMWI->getOperation();
|
|
switch(Op) {
|
|
case AtomicRMWInst::Add:
|
|
case AtomicRMWInst::Sub:
|
|
case AtomicRMWInst::Or:
|
|
case AtomicRMWInst::Xor:
|
|
return C->isZero();
|
|
case AtomicRMWInst::And:
|
|
return C->isMinusOne();
|
|
// FIXME: we could also treat Min/Max/UMin/UMax by the INT_MIN/INT_MAX/...
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool AtomicExpand::simplifyIdempotentRMW(AtomicRMWInst* RMWI) {
|
|
if (auto ResultingLoad = TLI->lowerIdempotentRMWIntoFencedLoad(RMWI)) {
|
|
if (TLI->shouldExpandAtomicLoadInIR(ResultingLoad))
|
|
expandAtomicLoad(ResultingLoad);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|