mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-14 04:57:33 +00:00
2661b411cc
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.7 KiB
TableGen
41 lines
1.7 KiB
TableGen
//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file defines the target-independent scheduling interfaces which should
|
|
// be implemented by each target which is using TableGen based scheduling.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/TargetItinerary.td"
|
|
|
|
// The SchedMachineModel is defined by subtargets for three categories of data:
|
|
// 1) Basic properties for coarse grained instruction cost model.
|
|
// 2) Scheduler Read/Write resources for simple per-opcode cost model.
|
|
// 3) Instruction itineraties for detailed reservation tables.
|
|
//
|
|
// Default values for basic properties are defined in MCSchedModel. "-1"
|
|
// indicates that the property is not overriden by the target description.
|
|
class SchedMachineModel {
|
|
int IssueWidth = -1; // Max instructions that may be scheduled per cycle.
|
|
int MinLatency = -1; // Determines which instrucions are allowed in a group.
|
|
// (-1) inorder (0) ooo, (1): inorder +var latencies.
|
|
int LoadLatency = -1; // Cycles for loads to access the cache.
|
|
int HighLatency = -1; // Approximation of cycles for "high latency" ops.
|
|
|
|
ProcessorItineraries Itineraries = NoItineraries;
|
|
|
|
bit NoModel = 0; // Special tag to indicate missing machine model.
|
|
}
|
|
|
|
def NoSchedModel : SchedMachineModel {
|
|
let NoModel = 1;
|
|
}
|
|
|
|
// TODO: Define classes for processor and scheduler resources.
|