llvm-6502/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
Jakob Stoklund Olesen a6f7499244 Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
Add an extra run with -regalloc=basic to keep them honest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 18:42:43 +00:00

67 lines
1.4 KiB
LLVM

;RUN: llc -march=sparc -regalloc=linearscan < %s | FileCheck %s -check-prefix=V8
;RUN: llc -march=sparc -regalloc=linearscan -mattr=v9 < %s | FileCheck %s -check-prefix=V9
; These tests depend on linear scan's trivial coalescer for reserved registers.
define i8* @frameaddr() nounwind readnone {
entry:
;V8: frameaddr
;V8: or %g0, %fp, {{.+}}
;V9: frameaddr
;V9: or %g0, %fp, {{.+}}
%0 = tail call i8* @llvm.frameaddress(i32 0)
ret i8* %0
}
define i8* @frameaddr2() nounwind readnone {
entry:
;V8: frameaddr2
;V8: ta 3
;V8: ld [%fp+56], {{.+}}
;V8: ld [{{.+}}+56], {{.+}}
;V8: ld [{{.+}}+56], {{.+}}
;V9: frameaddr2
;V9: flushw
;V9: ld [%fp+56], {{.+}}
;V9: ld [{{.+}}+56], {{.+}}
;V9: ld [{{.+}}+56], {{.+}}
%0 = tail call i8* @llvm.frameaddress(i32 3)
ret i8* %0
}
declare i8* @llvm.frameaddress(i32) nounwind readnone
define i8* @retaddr() nounwind readnone {
entry:
;V8: retaddr
;V8: or %g0, %i7, {{.+}}
;V9: retaddr
;V9: or %g0, %i7, {{.+}}
%0 = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %0
}
define i8* @retaddr2() nounwind readnone {
entry:
;V8: retaddr2
;V8: ta 3
;V8: ld [%fp+56], {{.+}}
;V8: ld [{{.+}}+56], {{.+}}
;V8: ld [{{.+}}+60], {{.+}}
;V9: retaddr2
;V9: flushw
;V9: ld [%fp+56], {{.+}}
;V9: ld [{{.+}}+56], {{.+}}
;V9: ld [{{.+}}+60], {{.+}}
%0 = tail call i8* @llvm.returnaddress(i32 3)
ret i8* %0
}
declare i8* @llvm.returnaddress(i32) nounwind readnone