mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 19:30:10 +00:00
e38bd53361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@585 91177308-0d34-0410-b5e6-96231b3b80d8
485 lines
14 KiB
C++
485 lines
14 KiB
C++
//***************************************************************************
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// File:
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// Sparc.cpp
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//
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// Purpose:
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//
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// History:
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// 7/15/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "llvm/Target/Sparc.h"
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#include "SparcInternals.h"
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#include "llvm/Method.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
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#include "llvm/CodeGen/PhyRegAlloc.h"
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// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
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//
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TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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//
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// Purpose:
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// Information about individual instructions.
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// Most information is stored in the SparcMachineInstrDesc array above.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class MachineInstrInfo.
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//---------------------------------------------------------------------------
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/*ctor*/
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UltraSparcInstrInfo::UltraSparcInstrInfo()
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: MachineInstrInfo(SparcMachineInstrDesc,
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/*descSize = */ NUM_TOTAL_OPCODES,
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/*numRealOpCodes = */ NUM_REAL_OPCODES)
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{
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}
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//---------------------------------------------------------------------------
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// class UltraSparcSchedInfo
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//
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// Purpose:
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// Scheduling information for the UltraSPARC.
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// Primarily just initializes machine-dependent parameters in
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// class MachineSchedInfo.
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//---------------------------------------------------------------------------
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/*ctor*/
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UltraSparcSchedInfo::UltraSparcSchedInfo(const MachineInstrInfo* mii)
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: MachineSchedInfo((unsigned int) SPARC_NUM_SCHED_CLASSES,
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mii,
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SparcRUsageDesc,
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SparcInstrUsageDeltas,
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SparcInstrIssueDeltas,
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sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
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sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
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{
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maxNumIssueTotal = 4;
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longestIssueConflict = 0; // computed from issuesGaps[]
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branchMispredictPenalty = 4; // 4 for SPARC IIi
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branchTargetUnknownPenalty = 2; // 2 for SPARC IIi
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l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi
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l1ICacheMissPenalty = 8; // ? for SPARC IIi
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inOrderLoads = true; // true for SPARC IIi
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inOrderIssue = true; // true for SPARC IIi
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inOrderExec = false; // false for most architectures
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inOrderRetire= true; // true for most architectures
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// must be called after above parameters are initialized.
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this->initializeResources();
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}
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void
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UltraSparcSchedInfo::initializeResources()
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{
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// Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
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MachineSchedInfo::initializeResources();
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// Machine-dependent fixups go here. None for now.
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}
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//---------------------------------------------------------------------------
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// class UltraSparcRegInfo
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//
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// Purpose:
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// This class provides info about sparc register classes.
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//--------------------------------------------------------------------------
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#if 0
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UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc *const USI ) :
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UltraSparcInfo(USI),
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NumOfIntArgRegs(6),
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NumOfFloatArgRegs(6)
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{
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MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
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MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
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assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 6 &&
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"6 Float regs are used for float arg passing");
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}
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// ***** TODO insert deletes for reg classes
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UltraSparcRegInfo::~UltraSparcRegInfo(void) { } // empty destructor
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#endif
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//---------------------------------------------------------------------------
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// UltraSparcRegInfo
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// Purpose:
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// This method will color incoming args to a method. If there are more
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// args than that can fit in regs, code will be inserted to pop them from
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// stack
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//---------------------------------------------------------------------------
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void UltraSparcRegInfo::colorArgs(const Method *const Meth,
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LiveRangeInfo& LRI) const
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{
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// get the argument list
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const Method::ArgumentListType& ArgList = Meth->getArgumentList();
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// get an iterator to arg list
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Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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unsigned intArgNo=0;
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// to keep track of which float regs are allocated for argument passing
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bool FloatArgUsedArr[NumOfFloatArgRegs];
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// init float arg used array
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for(unsigned i=0; i < NumOfFloatArgRegs; ++i)
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FloatArgUsedArr[i] = false;
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// for each argument
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for( ; ArgIt != ArgList.end() ; ++ArgIt) {
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// get the LR of arg
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LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
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unsigned RegClassID = (LR->getRegClass())->getID();
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// if the arg is in int class - allocate a reg for an int arg
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if( RegClassID == IntRegClassID ) {
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if( intArgNo < NumOfIntArgRegs) {
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LR->setColor( SparcIntRegOrder::i0 + intArgNo );
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if( DEBUG_RA) printReg( LR );
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}
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else {
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// TODO: Insert push code here
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assert( 0 && "Insert push code here!");
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}
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++intArgNo;
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}
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// if the arg is float/double
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else if ( RegClassID == FloatRegClassID) {
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if( LR->getTypeID() == Type::DoubleTyID ) {
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// find the first reg # we can pass a double arg
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for(unsigned i=0; i < NumOfFloatArgRegs; i+= 2) {
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if ( !FloatArgUsedArr[i] && !FloatArgUsedArr[i+1] ) {
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LR->setColor( SparcFloatRegOrder::f0 + i );
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FloatArgUsedArr[i] = true;
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FloatArgUsedArr[i+1] = true;
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if( DEBUG_RA) printReg( LR );
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break;
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}
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}
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if( ! LR->hasColor() ) { // if LR was not colored above
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assert(0 && "insert push code here for a double");
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}
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}
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else if( LR->getTypeID() == Type::FloatTyID ) {
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// find the first reg # we can pass a float arg
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for(unsigned i=0; i < NumOfFloatArgRegs; ++i) {
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if ( !FloatArgUsedArr[i] ) {
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LR->setColor( SparcFloatRegOrder::f0 + i );
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FloatArgUsedArr[i] = true;
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if( DEBUG_RA) printReg( LR );
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break;
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}
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}
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if( ! LR->hasColor() ) { // if LR was not colored above
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assert(0 && "insert push code here for a float");
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}
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}
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else
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assert(0 && "unknown float type in method arg");
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} // float register class
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else
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assert(0 && "Unknown RegClassID");
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}
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}
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void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
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unsigned RegClassID = (LR->getRegClass())->getID();
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cout << " *Node " << (LR->getUserIGNode())->getIndex();
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if( ! LR->hasColor() ) {
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cout << " - could not find a color" << endl;
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return;
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}
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// if a color is found
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cout << " colored with color "<< LR->getColor();
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if( RegClassID == IntRegClassID ) {
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cout<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) ;
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cout << "]" << endl;
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}
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else if ( RegClassID == FloatRegClassID) {
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cout << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
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if( LR->getTypeID() == Type::DoubleTyID )
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cout << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
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cout << "]" << endl;
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}
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}
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void UltraSparcRegInfo::colorCallArgs(vector<const Instruction *> &
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CallInstrList, LiveRangeInfo& LRI,
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AddedInstrMapType &AddedInstrMap) const
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{
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vector<const Instruction *>::const_iterator InstIt = CallInstrList.begin();
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for( ; InstIt != CallInstrList.end(); ++InstIt) {
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// Inst = LLVM call instruction
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const Instruction *const CallI = *InstIt;
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MachineCodeForVMInstr & MInstVec = CallI->getMachineInstrVec();
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MachineCodeForVMInstr::const_iterator MIIt = MInstVec.begin();
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// find the CALL/JMMPL machine instruction
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for( ; MIIt != MInstVec.end() &&
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! getUltraSparcInfo().getInstrInfo().isCall((*MIIt)->getOpCode());
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++MIIt );
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assert( (MIIt != MInstVec.end()) && "CALL/JMPL not found");
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// CallMI = CALL/JMPL machine isntruction
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const MachineInstr *const CallMI = *MIIt;
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Instruction::op_const_iterator OpIt = CallI->op_begin();
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unsigned intArgNo=0;
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//unsigned NumOfCallInterfs = LR->getNumOfCallInterferences();
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// to keep track of which float regs are allocated for argument passing
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bool FloatArgUsedArr[NumOfFloatArgRegs];
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// init float arg used array
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for(unsigned i=0; i < NumOfFloatArgRegs; ++i)
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FloatArgUsedArr[i] = false;
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// go thru all the operands of LLVM instruction
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for( ; OpIt != CallI->op_end(); ++OpIt ) {
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// get the LR of call operand (parameter)
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LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *OpIt);
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if ( !LR ) {
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cout << " Warning: In call instr, no LR for arg: " ;
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printValue(*OpIt);
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cout << endl;
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continue;
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}
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unsigned RegClassID = (LR->getRegClass())->getID();
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// if the arg is in int class - allocate a reg for an int arg
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if( RegClassID == IntRegClassID ) {
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if( intArgNo < NumOfIntArgRegs) {
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setCallArgColor( LR, SparcIntRegOrder::o0 + intArgNo );
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}
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else {
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// TODO: Insert push code here
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assert( 0 && "Insert push code here!");
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AddedInstrns * AI = AddedInstrMap[ CallMI ];
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if( ! AI ) AI = new AddedInstrns();
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// AI->InstrnsBefore.push_back( getStackPushInstr(LR) );
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AddedInstrMap[ CallMI ] = AI;
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}
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++intArgNo;
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}
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// if the arg is float/double
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else if ( RegClassID == FloatRegClassID) {
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if( LR->getTypeID() == Type::DoubleTyID ) {
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// find the first reg # we can pass a double arg
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for(unsigned i=0; i < NumOfFloatArgRegs; i+= 2) {
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if ( !FloatArgUsedArr[i] && !FloatArgUsedArr[i+1] ) {
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setCallArgColor(LR, SparcFloatRegOrder::f0 + i );
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FloatArgUsedArr[i] = true;
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FloatArgUsedArr[i+1] = true;
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//if( DEBUG_RA) printReg( LR );
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break;
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}
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}
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if( ! LR->hasColor() ) { // if LR was not colored above
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assert(0 && "insert push code here for a double");
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}
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}
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else if( LR->getTypeID() == Type::FloatTyID ) {
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// find the first reg # we can pass a float arg
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for(unsigned i=0; i < NumOfFloatArgRegs; ++i) {
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if ( !FloatArgUsedArr[i] ) {
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setCallArgColor(LR, SparcFloatRegOrder::f0 + i );
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FloatArgUsedArr[i] = true;
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// LR->setColor( SparcFloatRegOrder::f0 + i );
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// if( DEBUG_RA) printReg( LR );
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break;
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}
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}
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if( ! LR->hasColor() ) { // if LR was not colored above
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assert(0 && "insert push code here for a float");
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}
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}
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else
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assert(0 && "unknown float type in method arg");
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} // float register class
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else
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assert(0 && "Unknown RegClassID");
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} // for each operand in a call instruction
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} // for all call instrctions in CallInstrList
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}
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void UltraSparcRegInfo::setCallArgColor(LiveRange *const LR,
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const unsigned RegNo) const {
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// if no call interference and LR is NOT previously colored (e.g., as an
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// incoming arg)
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if( ! LR->getNumOfCallInterferences() && ! LR->hasColor() ) {
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// we can directly allocate a %o register
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LR->setColor( RegNo);
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if( DEBUG_RA) printReg( LR );
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}
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else { // there are call interferences
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/*
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// insert a copy machine instr to copy from LR to %o(reg)
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PreMInstrMap[ CallMI ] =
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getNewCopyMInstr( LR->, SparcIntRegOrder::o0 + intArgNo );
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*/
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cout << " $$$ TODO: Insert a copy for call argument!: " << endl;
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// We don't color LR here. It's colored as any other normal LR
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}
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}
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//---------------------------------------------------------------------------
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// class UltraSparcMachine
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//
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// Purpose:
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// Primary interface to machine description for the UltraSPARC.
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// Primarily just initializes machine-dependent parameters in
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// class TargetMachine, and creates machine-dependent subclasses
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// for classes such as MachineInstrInfo.
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//
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//---------------------------------------------------------------------------
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UltraSparc::UltraSparc() : TargetMachine("UltraSparc-Native"),
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InstSchedulingInfo(&InstInfo),
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RegInfo( this ) {
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optSizeForSubWordData = 4;
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minMemOpWordSize = 8;
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maxAtomicMemOpWordSize = 8;
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zeroRegNum = 0; // %g0 always gives 0 on Sparc
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}
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//----------------------------------------------------------------------------
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// Entry point for register allocation for a module
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//----------------------------------------------------------------------------
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void AllocateRegisters(Method *M, TargetMachine &TM)
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{
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if ( (M)->isExternal() ) // don't process prototypes
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return;
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if( DEBUG_RA ) {
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cout << endl << "******************** Method "<< (M)->getName();
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cout << " ********************" <<endl;
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}
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MethodLiveVarInfo LVI(M ); // Analyze live varaibles
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LVI.analyze();
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PhyRegAlloc PRA(M, TM , &LVI); // allocate registers
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PRA.allocateRegisters();
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if( DEBUG_RA ) cout << endl << "Register allocation complete!" << endl;
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}
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bool UltraSparc::compileMethod(Method *M) {
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if (SelectInstructionsForMethod(M, *this)) {
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cerr << "Instruction selection failed for method " << M->getName()
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<< "\n\n";
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return true;
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}
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if (ScheduleInstructionsWithSSA(M, *this, InstSchedulingInfo)) {
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cerr << "Instruction scheduling before allocation failed for method "
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<< M->getName() << "\n\n";
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return true;
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}
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AllocateRegisters(M, *this); // allocate registers
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return false;
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}
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