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https://github.com/c64scene-ar/llvm-6502.git
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7782102c70
LZCNT instructions are available. Force promotion to i32 to get a smaller encoding since the fix-ups necessary are just as complex for either promoted type We can't do standard promotion for CTLZ when lowering through BSR because it results in poor code surrounding the 'xor' at the end of this instruction. Essentially, if we promote the entire CTLZ node to i32, we end up doing the xor on a 32-bit CTLZ implementation, and then subtracting appropriately to get back to an i8 value. Instead, our custom logic just uses the knowledge of the incoming size to compute a perfect xor. I'd love to know of a way to fix this, but so far I'm drawing a blank. I suspect the legalizer could be more clever and/or it could collude with the DAG combiner, but how... ;] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251 91177308-0d34-0410-b5e6-96231b3b80d8
142 lines
2.9 KiB
LLVM
142 lines
2.9 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=yonah | FileCheck %s
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declare i8 @llvm.cttz.i8(i8, i1)
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declare i16 @llvm.cttz.i16(i16, i1)
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declare i32 @llvm.cttz.i32(i32, i1)
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declare i64 @llvm.cttz.i64(i64, i1)
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declare i8 @llvm.ctlz.i8(i8, i1)
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declare i16 @llvm.ctlz.i16(i16, i1)
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declare i32 @llvm.ctlz.i32(i32, i1)
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declare i64 @llvm.ctlz.i64(i64, i1)
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define i8 @cttz_i8(i8 %x) {
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%tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true )
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ret i8 %tmp
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; CHECK: cttz_i8:
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; CHECK: bsfl
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; CHECK-NOT: cmov
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; CHECK: ret
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}
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define i16 @cttz_i16(i16 %x) {
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%tmp = call i16 @llvm.cttz.i16( i16 %x, i1 true )
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ret i16 %tmp
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; CHECK: cttz_i16:
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; CHECK: bsfw
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; CHECK-NOT: cmov
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; CHECK: ret
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}
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define i32 @cttz_i32(i32 %x) {
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%tmp = call i32 @llvm.cttz.i32( i32 %x, i1 true )
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ret i32 %tmp
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; CHECK: cttz_i32:
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; CHECK: bsfl
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; CHECK-NOT: cmov
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; CHECK: ret
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}
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define i64 @cttz_i64(i64 %x) {
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%tmp = call i64 @llvm.cttz.i64( i64 %x, i1 true )
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ret i64 %tmp
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; CHECK: cttz_i64:
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; CHECK: bsfq
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; CHECK-NOT: cmov
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; CHECK: ret
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}
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define i8 @ctlz_i8(i8 %x) {
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entry:
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%tmp2 = call i8 @llvm.ctlz.i8( i8 %x, i1 true )
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ret i8 %tmp2
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; CHECK: ctlz_i8:
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; CHECK: bsrl
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; CHECK-NOT: cmov
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; CHECK: xorl $7,
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; CHECK: ret
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}
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define i16 @ctlz_i16(i16 %x) {
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entry:
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%tmp2 = call i16 @llvm.ctlz.i16( i16 %x, i1 true )
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ret i16 %tmp2
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; CHECK: ctlz_i16:
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; CHECK: bsrw
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; CHECK-NOT: cmov
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; CHECK: xorl $15,
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; CHECK: ret
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}
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define i32 @ctlz_i32(i32 %x) {
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%tmp = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
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ret i32 %tmp
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; CHECK: ctlz_i32:
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; CHECK: bsrl
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; CHECK-NOT: cmov
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; CHECK: xorl $31,
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; CHECK: ret
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}
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define i64 @ctlz_i64(i64 %x) {
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%tmp = call i64 @llvm.ctlz.i64( i64 %x, i1 true )
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ret i64 %tmp
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; CHECK: ctlz_i64:
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; CHECK: bsrq
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; CHECK-NOT: cmov
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; CHECK: xorq $63,
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; CHECK: ret
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}
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define i32 @ctlz_i32_cmov(i32 %n) {
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entry:
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; Generate a cmov to handle zero inputs when necessary.
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; CHECK: ctlz_i32_cmov:
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; CHECK: bsrl
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; CHECK: cmov
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; CHECK: xorl $31,
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; CHECK: ret
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%tmp1 = call i32 @llvm.ctlz.i32(i32 %n, i1 false)
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ret i32 %tmp1
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}
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define i32 @ctlz_i32_fold_cmov(i32 %n) {
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entry:
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; Don't generate the cmovne when the source is known non-zero (and bsr would
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; not set ZF).
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; rdar://9490949
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; CHECK: ctlz_i32_fold_cmov:
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; CHECK: bsrl
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; CHECK-NOT: cmov
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; CHECK: xorl $31,
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; CHECK: ret
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%or = or i32 %n, 1
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%tmp1 = call i32 @llvm.ctlz.i32(i32 %or, i1 false)
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ret i32 %tmp1
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}
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define i32 @ctlz_bsr(i32 %n) {
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entry:
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; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
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; the most significant bit, which is what 'bsr' does natively.
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; CHECK: ctlz_bsr:
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; CHECK: bsrl
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; CHECK-NOT: xorl
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; CHECK: ret
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%ctlz = call i32 @llvm.ctlz.i32(i32 %n, i1 true)
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%bsr = xor i32 %ctlz, 31
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ret i32 %bsr
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}
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define i32 @ctlz_bsr_cmov(i32 %n) {
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entry:
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; Same as ctlz_bsr, but ensure this happens even when there is a potential
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; zero.
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; CHECK: ctlz_bsr_cmov:
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; CHECK: bsrl
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; CHECK-NOT: xorl
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; CHECK: ret
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%ctlz = call i32 @llvm.ctlz.i32(i32 %n, i1 false)
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%bsr = xor i32 %ctlz, 31
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ret i32 %bsr
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}
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