mirror of
https://github.com/c64scene-ar/llvm-6502.git
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11ba3b1af6
subreg form on x86-64, to avoid the problem with x86-32 having GPRs that don't have 8-bit subregs. Also, change several 16-bit instructions to use equivalent 32-bit instructions. These have a smaller encoding and avoid partial-register updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54223 91177308-0d34-0410-b5e6-96231b3b80d8
52 lines
1.3 KiB
LLVM
52 lines
1.3 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86 | not grep and
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; RUN: llvm-as < %s | llc -march=x86-64 > %t
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; RUN: not grep and %t
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; RUN: not grep movzbq %t
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; RUN: not grep movzwq %t
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; RUN: not grep movzlq %t
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; These should use movzbl instead of 'and 255'.
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; This related to not having a ZERO_EXTEND_REG opcode.
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define i32 @c(i32 %d) nounwind {
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%e = add i32 %d, 1
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%retval = and i32 %e, 65535
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ret i32 %retval
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}
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define i64 @e(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 65535
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ret i64 %retval
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}
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define i64 @f(i64 %d) nounwind {
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%e = add i64 %d, 1
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%retval = and i64 %e, 4294967295
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ret i64 %retval
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}
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define i32 @g(i8 %d) nounwind {
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%e = add i8 %d, 1
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%retval = zext i8 %e to i32
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ret i32 %retval
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}
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define i32 @h(i16 %d) nounwind {
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%e = add i16 %d, 1
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%retval = zext i16 %e to i32
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ret i32 %retval
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}
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define i64 @i(i8 %d) nounwind {
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%e = add i8 %d, 1
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%retval = zext i8 %e to i64
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ret i64 %retval
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}
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define i64 @j(i16 %d) nounwind {
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%e = add i16 %d, 1
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%retval = zext i16 %e to i64
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ret i64 %retval
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}
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define i64 @k(i32 %d) nounwind {
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%e = add i32 %d, 1
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%retval = zext i32 %e to i64
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ret i64 %retval
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}
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