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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25932 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
3.8 KiB
C++
98 lines
3.8 KiB
C++
//===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV8 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8InstrInfo.h"
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#include "SparcV8.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "SparcV8GenInstrInfo.inc"
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using namespace llvm;
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SparcV8InstrInfo::SparcV8InstrInfo()
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: TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
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}
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static bool isZeroImmed (const MachineOperand &op) {
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return (op.isImmediate() && op.getImmedValue() == 0);
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg) const {
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// We look for 3 kinds of patterns here:
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// or with G0 or 0
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// add with G0 or 0
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// fmovs or FpMOVD (pseudo double move).
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if (MI.getOpcode() == V8::ORrr || MI.getOpcode() == V8::ADDrr) {
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if (MI.getOperand(1).getReg() == V8::G0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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return true;
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} else if (MI.getOperand (2).getReg() == V8::G0) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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} else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
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if (isZeroImmed(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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} else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned SparcV8InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == V8::LDri ||
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MI->getOpcode() == V8::LDFri ||
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MI->getOpcode() == V8::LDDFri) {
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if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned SparcV8InstrInfo::isStoreToStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == V8::STri ||
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MI->getOpcode() == V8::STFri ||
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MI->getOpcode() == V8::STDFri) {
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if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
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MI->getOperand(1).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(0).getFrameIndex();
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return MI->getOperand(2).getReg();
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}
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}
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return 0;
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}
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