mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2d0eef4c7d
This includes instructions with aggregate operands (insert/extract), instructions with vector operands (insert/extract/shuffle), binary arithmetic and bitwise instructions, conversion instructions and terminators. Work was done by lama.saba@intel.com. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202262 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
3.0 KiB
LLVM
121 lines
3.0 KiB
LLVM
; RUN: llvm-dis < %s.bc| FileCheck %s
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; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
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; The test checks that LLVM does not misread binary float instructions from
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; older bitcode files.
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define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
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entry:
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; CHECK: %res1 = fadd float %x1, %x1
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%res1 = fadd float %x1, %x1
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; CHECK-NEXT: %res2 = fadd double %x2, %x2
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%res2 = fadd double %x2, %x2
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; CHECK-NEXT: %res3 = fadd half %x3, %x3
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%res3 = fadd half %x3, %x3
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; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4
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%res4 = fadd fp128 %x4, %x4
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; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5
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%res5 = fadd x86_fp80 %x5, %x5
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; CHECK-NEXT: %res6 = fadd ppc_fp128 %x6, %x6
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%res6 = fadd ppc_fp128 %x6, %x6
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ret void
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}
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define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){
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entry:
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; CHECK: %res1 = fadd <2 x float> %x1, %x1
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%res1 = fadd <2 x float> %x1, %x1
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; CHECK-NEXT: %res2 = fadd <3 x float> %x2, %x2
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%res2 = fadd <3 x float> %x2, %x2
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; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3
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%res3 = fadd <4 x float> %x3, %x3
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; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4
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%res4 = fadd <8 x float> %x4, %x4
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; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5
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%res5 = fadd <16 x float> %x5, %x5
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ret void
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}
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define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){
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entry:
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; CHECK: %res1 = fadd <2 x double> %x1, %x1
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%res1 = fadd <2 x double> %x1, %x1
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; CHECK-NEXT: %res2 = fadd <3 x double> %x2, %x2
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%res2 = fadd <3 x double> %x2, %x2
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; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3
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%res3 = fadd <4 x double> %x3, %x3
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; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4
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%res4 = fadd <8 x double> %x4, %x4
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; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5
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%res5 = fadd <16 x double> %x5, %x5
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ret void
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}
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define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){
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entry:
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; CHECK: %res1 = fadd <2 x half> %x1, %x1
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%res1 = fadd <2 x half> %x1, %x1
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; CHECK-NEXT: %res2 = fadd <3 x half> %x2, %x2
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%res2 = fadd <3 x half> %x2, %x2
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; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3
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%res3 = fadd <4 x half> %x3, %x3
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; CHECK-NEXT: %res4 = fadd <8 x half> %x4, %x4
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%res4 = fadd <8 x half> %x4, %x4
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; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5
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%res5 = fadd <16 x half> %x5, %x5
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ret void
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}
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define void @fsub(float %x1){
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entry:
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; CHECK: %res1 = fsub float %x1, %x1
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%res1 = fsub float %x1, %x1
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ret void
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}
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define void @fmul(float %x1){
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entry:
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; CHECK: %res1 = fmul float %x1, %x1
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%res1 = fmul float %x1, %x1
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ret void
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}
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define void @fdiv(float %x1){
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entry:
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; CHECK: %res1 = fdiv float %x1, %x1
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%res1 = fdiv float %x1, %x1
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ret void
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}
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define void @frem(float %x1){
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entry:
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; CHECK: %res1 = frem float %x1, %x1
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%res1 = frem float %x1, %x1
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ret void
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}
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