llvm-6502/test/Bitcode/cmpxchg-upgrade.ll
Tim Northover ca396e391e IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like:

	cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic

where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).

rdar://problem/15996804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-11 10:48:52 +00:00

23 lines
735 B
LLVM

; RUN: llvm-dis < %s.bc | FileCheck %s
; cmpxchg-upgrade.ll.bc was produced by running a version of llvm-as from just
; before the IR change on this file.
define void @test(i32* %addr) {
cmpxchg i32* %addr, i32 42, i32 0 monotonic
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 monotonic monotonic
cmpxchg i32* %addr, i32 42, i32 0 acquire
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 acquire acquire
cmpxchg i32* %addr, i32 42, i32 0 release
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 release monotonic
cmpxchg i32* %addr, i32 42, i32 0 acq_rel
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 acq_rel acquire
cmpxchg i32* %addr, i32 42, i32 0 seq_cst
; CHECK: cmpxchg i32* %addr, i32 42, i32 0 seq_cst seq_cst
ret void
}