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https://github.com/c64scene-ar/llvm-6502.git
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e45aa737ba
Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of CRRC seems to cause failures as well. Further investigation is required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28097 91177308-0d34-0410-b5e6-96231b3b80d8
599 lines
25 KiB
C++
599 lines
25 KiB
C++
//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCRegisterInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineDebugInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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#include <iostream>
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using namespace llvm;
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// PPC::F14, return the number that it corresponds to (e.g. 14).
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unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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switch (RegEnum) {
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case PPC::R0 : case PPC::F0 : case PPC::V0 : case PPC::CR0: return 0;
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case PPC::R1 : case PPC::F1 : case PPC::V1 : case PPC::CR1: return 1;
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case PPC::R2 : case PPC::F2 : case PPC::V2 : case PPC::CR2: return 2;
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case PPC::R3 : case PPC::F3 : case PPC::V3 : case PPC::CR3: return 3;
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case PPC::R4 : case PPC::F4 : case PPC::V4 : case PPC::CR4: return 4;
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case PPC::R5 : case PPC::F5 : case PPC::V5 : case PPC::CR5: return 5;
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case PPC::R6 : case PPC::F6 : case PPC::V6 : case PPC::CR6: return 6;
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case PPC::R7 : case PPC::F7 : case PPC::V7 : case PPC::CR7: return 7;
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case PPC::R8 : case PPC::F8 : case PPC::V8 : return 8;
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case PPC::R9 : case PPC::F9 : case PPC::V9 : return 9;
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case PPC::R10: case PPC::F10: case PPC::V10: return 10;
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case PPC::R11: case PPC::F11: case PPC::V11: return 11;
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case PPC::R12: case PPC::F12: case PPC::V12: return 12;
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case PPC::R13: case PPC::F13: case PPC::V13: return 13;
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case PPC::R14: case PPC::F14: case PPC::V14: return 14;
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case PPC::R15: case PPC::F15: case PPC::V15: return 15;
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case PPC::R16: case PPC::F16: case PPC::V16: return 16;
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case PPC::R17: case PPC::F17: case PPC::V17: return 17;
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case PPC::R18: case PPC::F18: case PPC::V18: return 18;
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case PPC::R19: case PPC::F19: case PPC::V19: return 19;
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case PPC::R20: case PPC::F20: case PPC::V20: return 20;
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case PPC::R21: case PPC::F21: case PPC::V21: return 21;
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case PPC::R22: case PPC::F22: case PPC::V22: return 22;
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case PPC::R23: case PPC::F23: case PPC::V23: return 23;
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case PPC::R24: case PPC::F24: case PPC::V24: return 24;
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case PPC::R25: case PPC::F25: case PPC::V25: return 25;
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case PPC::R26: case PPC::F26: case PPC::V26: return 26;
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case PPC::R27: case PPC::F27: case PPC::V27: return 27;
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case PPC::R28: case PPC::F28: case PPC::V28: return 28;
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case PPC::R29: case PPC::F29: case PPC::V29: return 29;
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case PPC::R30: case PPC::F30: case PPC::V30: return 30;
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case PPC::R31: case PPC::F31: case PPC::V31: return 31;
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default:
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std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
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abort();
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}
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}
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PPCRegisterInfo::PPCRegisterInfo()
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: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
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}
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void
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PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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if (SrcReg == PPC::LR) {
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// FIXME: this spills LR immediately to memory in one step. To do this, we
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// use R11, which we know cannot be used in the prolog/epilog. This is a
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// hack.
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BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
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} else if (RC == PPC::CRRCRegisterClass) {
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BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
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} else if (RC == PPC::GPRCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::G8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::F8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
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BuildMI(MBB, MI, PPC::STVX, 3)
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.addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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}
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void
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PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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if (DestReg == PPC::LR) {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
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BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
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} else if (RC == PPC::CRRCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
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BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
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} else if (RC == PPC::GPRCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
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} else if (RC == PPC::G8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
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} else if (RC == PPC::F8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
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BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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}
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void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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if (RC == PPC::GPRCRegisterClass) {
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BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PPC::G8RCRegisterClass) {
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BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PPC::F4RCRegisterClass) {
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BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
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} else if (RC == PPC::F8RCRegisterClass) {
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BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
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} else if (RC == PPC::CRRCRegisterClass) {
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BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
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} else if (RC == PPC::VRRCRegisterClass) {
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BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else {
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std::cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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}
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/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
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/// copy instructions, turning them into load/store instructions.
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MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
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unsigned OpNum,
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int FrameIndex) const {
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// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
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// it takes more than one instruction to store it.
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unsigned Opc = MI->getOpcode();
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if ((Opc == PPC::OR4 &&
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MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STW,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
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}
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} else if ((Opc == PPC::OR8 &&
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MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STD,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex);
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}
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} else if (Opc == PPC::FMRD) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STFD,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
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}
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} else if (Opc == PPC::FMRS) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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return addFrameReference(BuildMI(PPC::STFS,
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3).addReg(InReg), FrameIndex);
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} else { // move -> load
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unsigned OutReg = MI->getOperand(0).getReg();
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return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
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}
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}
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return 0;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(const MachineFunction &MF) {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
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// If frame pointers are forced, or if there are variable sized stack objects,
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// use a frame pointer.
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//
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return NoFramePointerElim || MFI->hasVarSizedObjects();
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}
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void PPCRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (hasFP(MF)) {
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// If we have a frame pointer, convert as follows:
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// ADJCALLSTACKDOWN -> addi, r1, r1, -amount
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// ADJCALLSTACKUP -> addi, r1, r1, amount
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MachineInstr *Old = I;
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unsigned Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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// Replace the pseudo instruction with a new instruction...
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if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
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BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount);
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} else {
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assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
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BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount);
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}
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}
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}
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MBB.erase(I);
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}
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void
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PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
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MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
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// Take into account whether it's an add or mem instruction
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unsigned OffIdx = (i == 2) ? 1 : 2;
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// Now add the frame object offset to the offset from r1.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(OffIdx).getImmedValue();
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// If we're not using a Frame Pointer that has been set to the value of the
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// SP before having the stack size subtracted from it, then add the stack size
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// to Offset to get the correct offset.
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Offset += MF.getFrameInfo()->getStackSize();
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if (Offset > 32767 || Offset < -32768) {
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// Insert a set of r0 with the full offset value before the ld, st, or add
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MachineBasicBlock *MBB = MI.getParent();
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BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16);
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BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
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// convert into indexed form of the instruction
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// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
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// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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assert(ImmToIdxMap.count(MI.getOpcode()) &&
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"No indexed form of load or store available!");
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unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
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MI.setOpcode(NewOpcode);
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MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
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MI.SetMachineOperandReg(2, PPC::R0);
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} else {
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switch (MI.getOpcode()) {
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case PPC::LWA:
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case PPC::LD:
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case PPC::STD:
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case PPC::STD_32:
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assert((Offset & 3) == 0 && "Invalid frame offset!");
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Offset >>= 2; // The actual encoded value has the low two bits zero.
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break;
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}
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MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
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Offset);
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}
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}
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/// VRRegNo - Map from a numbered VR register to its enum value.
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///
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static const unsigned short VRRegNo[] = {
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PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
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PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
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PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
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PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
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};
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/// RemoveVRSaveCode - We have found that this function does not need any code
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/// to manipulate the VRSAVE register, even though it uses vector registers.
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/// This can happen when the only registers used are known to be live in or out
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/// of the function. Remove all of the VRSAVE related code from the function.
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static void RemoveVRSaveCode(MachineInstr *MI) {
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MachineBasicBlock *Entry = MI->getParent();
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MachineFunction *MF = Entry->getParent();
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// We know that the MTVRSAVE instruction immediately follows MI. Remove it.
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MachineBasicBlock::iterator MBBI = MI;
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++MBBI;
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assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
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MBBI->eraseFromParent();
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bool RemovedAllMTVRSAVEs = true;
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// See if we can find and remove the MTVRSAVE instruction from all of the
|
|
// epilog blocks.
|
|
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
|
|
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
|
|
// If last instruction is a return instruction, add an epilogue
|
|
if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
|
|
bool FoundIt = false;
|
|
for (MBBI = I->end(); MBBI != I->begin(); ) {
|
|
--MBBI;
|
|
if (MBBI->getOpcode() == PPC::MTVRSAVE) {
|
|
MBBI->eraseFromParent(); // remove it.
|
|
FoundIt = true;
|
|
break;
|
|
}
|
|
}
|
|
RemovedAllMTVRSAVEs &= FoundIt;
|
|
}
|
|
}
|
|
|
|
// If we found and removed all MTVRSAVE instructions, remove the read of
|
|
// VRSAVE as well.
|
|
if (RemovedAllMTVRSAVEs) {
|
|
MBBI = MI;
|
|
assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
|
|
--MBBI;
|
|
assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
|
|
MBBI->eraseFromParent();
|
|
}
|
|
|
|
// Finally, nuke the UPDATE_VRSAVE.
|
|
MI->eraseFromParent();
|
|
}
|
|
|
|
// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
|
|
// instruction selector. Based on the vector registers that have been used,
|
|
// transform this into the appropriate ORI instruction.
|
|
static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
|
|
unsigned UsedRegMask = 0;
|
|
for (unsigned i = 0; i != 32; ++i)
|
|
if (UsedRegs[VRRegNo[i]])
|
|
UsedRegMask |= 1 << (31-i);
|
|
|
|
// Live in and live out values already must be in the mask, so don't bother
|
|
// marking them.
|
|
MachineFunction *MF = MI->getParent()->getParent();
|
|
for (MachineFunction::livein_iterator I =
|
|
MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
|
|
unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
|
|
if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
|
|
UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
|
|
}
|
|
for (MachineFunction::liveout_iterator I =
|
|
MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
|
|
unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
|
|
if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
|
|
UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
|
|
}
|
|
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
// If no registers are used, turn this into a copy.
|
|
if (UsedRegMask == 0) {
|
|
// Remove all VRSAVE code.
|
|
RemoveVRSaveCode(MI);
|
|
return;
|
|
} else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
|
|
BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
|
|
.addReg(SrcReg).addImm(UsedRegMask);
|
|
} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
|
|
BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
|
|
.addReg(SrcReg).addImm(UsedRegMask >> 16);
|
|
} else {
|
|
BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
|
|
.addReg(SrcReg).addImm(UsedRegMask >> 16);
|
|
BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
|
|
.addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
|
|
}
|
|
|
|
// Remove the old UPDATE_VRSAVE instruction.
|
|
MI->eraseFromParent();
|
|
}
|
|
|
|
|
|
void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
|
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo();
|
|
|
|
// Do we have a frame pointer for this function?
|
|
bool HasFP = hasFP(MF);
|
|
|
|
// Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
|
|
// process it.
|
|
for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
|
|
if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
|
|
HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Move MBBI back to the beginning of the function.
|
|
MBBI = MBB.begin();
|
|
|
|
// Get the number of bytes to allocate from the FrameInfo
|
|
unsigned NumBytes = MFI->getStackSize();
|
|
|
|
// Get the alignments provided by the target, and the maximum alignment
|
|
// (if any) of the fixed frame objects.
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
unsigned MaxAlign = MFI->getMaxAlignment();
|
|
|
|
// If we have calls, we cannot use the red zone to store callee save registers
|
|
// and we must set up a stack frame, so calculate the necessary size here.
|
|
if (MFI->hasCalls()) {
|
|
// We reserve argument space for call sites in the function immediately on
|
|
// entry to the current function. This eliminates the need for add/sub
|
|
// brackets around call sites.
|
|
NumBytes += MFI->getMaxCallFrameSize();
|
|
}
|
|
|
|
// If we are a leaf function, and use up to 224 bytes of stack space,
|
|
// and don't have a frame pointer, then we do not need to adjust the stack
|
|
// pointer (we fit in the Red Zone).
|
|
if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() &&
|
|
MaxAlign <= TargetAlign)) {
|
|
MFI->setStackSize(0);
|
|
return;
|
|
}
|
|
|
|
// Add the size of R1 to NumBytes size for the store of R1 to the bottom
|
|
// of the stack and round the size to a multiple of the alignment.
|
|
unsigned Align = std::max(TargetAlign, MaxAlign);
|
|
unsigned GPRSize = 4;
|
|
unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize;
|
|
NumBytes = (NumBytes+Size+Align-1)/Align*Align;
|
|
|
|
// Update frame info to pretend that this is part of the stack...
|
|
MFI->setStackSize(NumBytes);
|
|
int NegNumbytes = -NumBytes;
|
|
|
|
// Adjust stack pointer: r1 -= numbytes.
|
|
// If there is a preferred stack alignment, align R1 now
|
|
if (MaxAlign > TargetAlign) {
|
|
assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!");
|
|
assert(isInt16(MaxAlign-NumBytes) && "Unhandled stack size and alignment!");
|
|
BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
|
|
.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
|
|
BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
|
|
.addSImm(MaxAlign-NumBytes);
|
|
BuildMI(MBB, MBBI, PPC::STWUX, 3)
|
|
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
|
|
} else if (NumBytes <= 32768) {
|
|
BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addSImm(NegNumbytes)
|
|
.addReg(PPC::R1);
|
|
} else {
|
|
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
|
|
BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
|
|
.addImm(NegNumbytes & 0xFFFF);
|
|
BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
|
|
.addReg(PPC::R0);
|
|
}
|
|
|
|
if (DebugInfo && DebugInfo->hasInfo()) {
|
|
std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves();
|
|
unsigned LabelID = DebugInfo->NextLabelID();
|
|
|
|
// Show update of SP.
|
|
MachineLocation Dst(MachineLocation::VirtualFP);
|
|
MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes);
|
|
Moves.push_back(new MachineMove(LabelID, Dst, Src));
|
|
|
|
BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addSImm(LabelID);
|
|
}
|
|
|
|
// If there is a frame pointer, copy R1 (SP) into R31 (FP)
|
|
if (HasFP) {
|
|
BuildMI(MBB, MBBI, PPC::STW, 3)
|
|
.addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
|
|
BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
|
|
}
|
|
}
|
|
|
|
void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
assert(MBBI->getOpcode() == PPC::BLR &&
|
|
"Can only insert epilog into returning blocks");
|
|
|
|
// Get alignment info so we know how to restore r1
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
|
|
// Get the number of bytes allocated from the FrameInfo.
|
|
unsigned NumBytes = MFI->getStackSize();
|
|
unsigned GPRSize = 4;
|
|
|
|
if (NumBytes != 0) {
|
|
// If this function has a frame pointer, load the saved stack pointer from
|
|
// its stack slot.
|
|
if (hasFP(MF)) {
|
|
BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
|
|
.addSImm(GPRSize).addReg(PPC::R31);
|
|
}
|
|
|
|
// The loaded (or persistent) stack pointer value is offseted by the 'stwu'
|
|
// on entry to the function. Add this offset back now.
|
|
if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) {
|
|
BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
|
|
.addReg(PPC::R1).addSImm(NumBytes);
|
|
} else {
|
|
BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned PPCRegisterInfo::getRARegister() const {
|
|
return PPC::LR;
|
|
}
|
|
|
|
unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
|
|
return hasFP(MF) ? PPC::R31 : PPC::R1;
|
|
}
|
|
|
|
void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves)
|
|
const {
|
|
// Initial state is the frame pointer is R1.
|
|
MachineLocation Dst(MachineLocation::VirtualFP);
|
|
MachineLocation Src(PPC::R1, 0);
|
|
Moves.push_back(new MachineMove(0, Dst, Src));
|
|
}
|
|
|
|
#include "PPCGenRegisterInfo.inc"
|
|
|