Jim Grosbach 4a5ffb399f ARM SSAT instruction 5-bit immediate handling. ... The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-22 23:16:18 +00:00
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ARMDisassembler.cpp	Fix typo in the comment.	2011-04-19 23:58:52 +00:00
ARMDisassembler.h	Better error handling of invalid IT mask '0000', instead of just asserting.	2010-04-19 23:02:58 +00:00
ARMDisassemblerCore.cpp	ARM SSAT instruction 5-bit immediate handling.	2011-07-22 23:16:18 +00:00
ARMDisassemblerCore.h	Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.	2011-07-21 23:38:37 +00:00
CMakeLists.txt	CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86.	2010-12-29 03:59:27 +00:00
Makefile	Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in	2010-04-07 20:53:12 +00:00
ThumbDisassemblerCore.h	ARM SSAT instruction 5-bit immediate handling.	2011-07-22 23:16:18 +00:00