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The ExecutionDepsFix previously mapped each register to 1 or zero registers of the register class it was called with and therefore simulating liveness for. This was problematic for cases involving wider registers like Q0 on ARM where ExecutionDepsFix gets invoked for the Dxx registers. In these cases the wide register would get mapped to the last matching D register, while it should have been all matching D registers. This commit changes the AliasMap to use a SmallVector to map registers to potentially multiple destination regclass registers. This is required to avoid regressions with subregister liveness tracking enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224447 91177308-0d34-0410-b5e6-96231b3b80d8
808 lines
26 KiB
C++
808 lines
26 KiB
C++
//===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the execution dependency fix pass.
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//
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// Some X86 SSE instructions like mov, and, or, xor are available in different
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// variants for different operand types. These variant instructions are
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// equivalent, but on Nehalem and newer cpus there is extra latency
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// transferring data between integer and floating point domains. ARM cores
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// have similar issues when they are configured with both VFP and NEON
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// pipelines.
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//
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// This pass changes the variant instructions to minimize domain crossings.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Allocator.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "execution-fix"
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/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
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/// of execution domains.
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///
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/// An open DomainValue represents a set of instructions that can still switch
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/// execution domain. Multiple registers may refer to the same open
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/// DomainValue - they will eventually be collapsed to the same execution
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/// domain.
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///
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/// A collapsed DomainValue represents a single register that has been forced
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/// into one of more execution domains. There is a separate collapsed
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/// DomainValue for each register, but it may contain multiple execution
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/// domains. A register value is initially created in a single execution
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/// domain, but if we were forced to pay the penalty of a domain crossing, we
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/// keep track of the fact that the register is now available in multiple
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/// domains.
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namespace {
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struct DomainValue {
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// Basic reference counting.
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unsigned Refs;
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// Bitmask of available domains. For an open DomainValue, it is the still
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// possible domains for collapsing. For a collapsed DomainValue it is the
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// domains where the register is available for free.
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unsigned AvailableDomains;
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// Pointer to the next DomainValue in a chain. When two DomainValues are
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// merged, Victim.Next is set to point to Victor, so old DomainValue
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// references can be updated by following the chain.
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DomainValue *Next;
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// Twiddleable instructions using or defining these registers.
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SmallVector<MachineInstr*, 8> Instrs;
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// A collapsed DomainValue has no instructions to twiddle - it simply keeps
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// track of the domains where the registers are already available.
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bool isCollapsed() const { return Instrs.empty(); }
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// Is domain available?
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bool hasDomain(unsigned domain) const {
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assert(domain <
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static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
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"undefined behavior");
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return AvailableDomains & (1u << domain);
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}
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// Mark domain as available.
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void addDomain(unsigned domain) {
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AvailableDomains |= 1u << domain;
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}
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// Restrict to a single domain available.
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void setSingleDomain(unsigned domain) {
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AvailableDomains = 1u << domain;
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}
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// Return bitmask of domains that are available and in mask.
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unsigned getCommonDomains(unsigned mask) const {
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return AvailableDomains & mask;
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}
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// First domain available.
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unsigned getFirstDomain() const {
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return countTrailingZeros(AvailableDomains);
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}
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DomainValue() : Refs(0) { clear(); }
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// Clear this DomainValue and point to next which has all its data.
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void clear() {
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AvailableDomains = 0;
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Next = nullptr;
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Instrs.clear();
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}
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};
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}
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namespace {
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/// LiveReg - Information about a live register.
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struct LiveReg {
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/// Value currently in this register, or NULL when no value is being tracked.
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/// This counts as a DomainValue reference.
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DomainValue *Value;
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/// Instruction that defined this register, relative to the beginning of the
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/// current basic block. When a LiveReg is used to represent a live-out
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/// register, this value is relative to the end of the basic block, so it
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/// will be a negative number.
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int Def;
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};
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} // anonynous namespace
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namespace {
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class ExeDepsFix : public MachineFunctionPass {
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static char ID;
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SpecificBumpPtrAllocator<DomainValue> Allocator;
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SmallVector<DomainValue*,16> Avail;
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const TargetRegisterClass *const RC;
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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std::vector<SmallVector<int, 1>> AliasMap;
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const unsigned NumRegs;
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LiveReg *LiveRegs;
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typedef DenseMap<MachineBasicBlock*, LiveReg*> LiveOutMap;
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LiveOutMap LiveOuts;
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/// List of undefined register reads in this block in forward order.
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std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
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/// Storage for register unit liveness.
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LivePhysRegs LiveRegSet;
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/// Current instruction number.
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/// The first instruction in each basic block is 0.
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int CurInstr;
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/// True when the current block has a predecessor that hasn't been visited
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/// yet.
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bool SeenUnknownBackEdge;
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public:
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ExeDepsFix(const TargetRegisterClass *rc)
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: MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "Execution dependency fix";
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}
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private:
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iterator_range<SmallVectorImpl<int>::const_iterator>
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regIndizes(unsigned Reg) const;
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// DomainValue allocation.
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DomainValue *alloc(int domain = -1);
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DomainValue *retain(DomainValue *DV) {
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if (DV) ++DV->Refs;
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return DV;
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}
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void release(DomainValue*);
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DomainValue *resolve(DomainValue*&);
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// LiveRegs manipulations.
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void setLiveReg(int rx, DomainValue *DV);
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void kill(int rx);
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void force(int rx, unsigned domain);
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void collapse(DomainValue *dv, unsigned domain);
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bool merge(DomainValue *A, DomainValue *B);
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void enterBasicBlock(MachineBasicBlock*);
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void leaveBasicBlock(MachineBasicBlock*);
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void visitInstr(MachineInstr*);
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void processDefs(MachineInstr*, bool Kill);
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void visitSoftInstr(MachineInstr*, unsigned mask);
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void visitHardInstr(MachineInstr*, unsigned domain);
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bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
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void processUndefReads(MachineBasicBlock*);
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};
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}
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char ExeDepsFix::ID = 0;
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/// Translate TRI register number to a list of indizes into our stmaller tables
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/// of interesting registers.
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iterator_range<SmallVectorImpl<int>::const_iterator>
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ExeDepsFix::regIndizes(unsigned Reg) const {
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assert(Reg < AliasMap.size() && "Invalid register");
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const auto &Entry = AliasMap[Reg];
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return make_range(Entry.begin(), Entry.end());
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}
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DomainValue *ExeDepsFix::alloc(int domain) {
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DomainValue *dv = Avail.empty() ?
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new(Allocator.Allocate()) DomainValue :
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Avail.pop_back_val();
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if (domain >= 0)
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dv->addDomain(domain);
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assert(dv->Refs == 0 && "Reference count wasn't cleared");
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assert(!dv->Next && "Chained DomainValue shouldn't have been recycled");
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return dv;
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}
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/// release - Release a reference to DV. When the last reference is released,
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/// collapse if needed.
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void ExeDepsFix::release(DomainValue *DV) {
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while (DV) {
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assert(DV->Refs && "Bad DomainValue");
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if (--DV->Refs)
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return;
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// There are no more DV references. Collapse any contained instructions.
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if (DV->AvailableDomains && !DV->isCollapsed())
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collapse(DV, DV->getFirstDomain());
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DomainValue *Next = DV->Next;
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DV->clear();
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Avail.push_back(DV);
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// Also release the next DomainValue in the chain.
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DV = Next;
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}
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}
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/// resolve - Follow the chain of dead DomainValues until a live DomainValue is
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/// reached. Update the referenced pointer when necessary.
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DomainValue *ExeDepsFix::resolve(DomainValue *&DVRef) {
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DomainValue *DV = DVRef;
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if (!DV || !DV->Next)
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return DV;
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// DV has a chain. Find the end.
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do DV = DV->Next;
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while (DV->Next);
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// Update DVRef to point to DV.
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retain(DV);
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release(DVRef);
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DVRef = DV;
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return DV;
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}
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/// Set LiveRegs[rx] = dv, updating reference counts.
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void ExeDepsFix::setLiveReg(int rx, DomainValue *dv) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(LiveRegs && "Must enter basic block first.");
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if (LiveRegs[rx].Value == dv)
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return;
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if (LiveRegs[rx].Value)
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release(LiveRegs[rx].Value);
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LiveRegs[rx].Value = retain(dv);
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}
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// Kill register rx, recycle or collapse any DomainValue.
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void ExeDepsFix::kill(int rx) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(LiveRegs && "Must enter basic block first.");
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if (!LiveRegs[rx].Value)
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return;
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release(LiveRegs[rx].Value);
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LiveRegs[rx].Value = nullptr;
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}
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/// Force register rx into domain.
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void ExeDepsFix::force(int rx, unsigned domain) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(LiveRegs && "Must enter basic block first.");
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if (DomainValue *dv = LiveRegs[rx].Value) {
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if (dv->isCollapsed())
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dv->addDomain(domain);
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else if (dv->hasDomain(domain))
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collapse(dv, domain);
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else {
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// This is an incompatible open DomainValue. Collapse it to whatever and
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// force the new value into domain. This costs a domain crossing.
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collapse(dv, dv->getFirstDomain());
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assert(LiveRegs[rx].Value && "Not live after collapse?");
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LiveRegs[rx].Value->addDomain(domain);
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}
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} else {
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// Set up basic collapsed DomainValue.
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setLiveReg(rx, alloc(domain));
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}
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}
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/// Collapse open DomainValue into given domain. If there are multiple
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/// registers using dv, they each get a unique collapsed DomainValue.
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void ExeDepsFix::collapse(DomainValue *dv, unsigned domain) {
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assert(dv->hasDomain(domain) && "Cannot collapse");
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// Collapse all the instructions.
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while (!dv->Instrs.empty())
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TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain);
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dv->setSingleDomain(domain);
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// If there are multiple users, give them new, unique DomainValues.
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if (LiveRegs && dv->Refs > 1)
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for (unsigned rx = 0; rx != NumRegs; ++rx)
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if (LiveRegs[rx].Value == dv)
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setLiveReg(rx, alloc(domain));
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}
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/// Merge - All instructions and registers in B are moved to A, and B is
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/// released.
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bool ExeDepsFix::merge(DomainValue *A, DomainValue *B) {
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assert(!A->isCollapsed() && "Cannot merge into collapsed");
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assert(!B->isCollapsed() && "Cannot merge from collapsed");
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if (A == B)
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return true;
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// Restrict to the domains that A and B have in common.
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unsigned common = A->getCommonDomains(B->AvailableDomains);
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if (!common)
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return false;
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A->AvailableDomains = common;
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A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
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// Clear the old DomainValue so we won't try to swizzle instructions twice.
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B->clear();
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// All uses of B are referred to A.
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B->Next = retain(A);
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for (unsigned rx = 0; rx != NumRegs; ++rx) {
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assert(LiveRegs && "no space allocated for live registers");
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if (LiveRegs[rx].Value == B)
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setLiveReg(rx, A);
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}
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return true;
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}
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// enterBasicBlock - Set up LiveRegs by merging predecessor live-out values.
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void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
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// Detect back-edges from predecessors we haven't processed yet.
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SeenUnknownBackEdge = false;
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// Reset instruction counter in each basic block.
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CurInstr = 0;
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// Set up UndefReads to track undefined register reads.
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UndefReads.clear();
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LiveRegSet.clear();
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// Set up LiveRegs to represent registers entering MBB.
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if (!LiveRegs)
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LiveRegs = new LiveReg[NumRegs];
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// Default values are 'nothing happened a long time ago'.
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for (unsigned rx = 0; rx != NumRegs; ++rx) {
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LiveRegs[rx].Value = nullptr;
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LiveRegs[rx].Def = -(1 << 20);
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}
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// This is the entry block.
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if (MBB->pred_empty()) {
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for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
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e = MBB->livein_end(); i != e; ++i) {
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for (int rx : regIndizes(*i)) {
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// Treat function live-ins as if they were defined just before the first
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// instruction. Usually, function arguments are set up immediately
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// before the call.
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LiveRegs[rx].Def = -1;
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}
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}
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DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
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return;
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}
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
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pe = MBB->pred_end(); pi != pe; ++pi) {
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LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
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if (fi == LiveOuts.end()) {
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SeenUnknownBackEdge = true;
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continue;
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}
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assert(fi->second && "Can't have NULL entries");
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for (unsigned rx = 0; rx != NumRegs; ++rx) {
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// Use the most recent predecessor def for each register.
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LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);
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DomainValue *pdv = resolve(fi->second[rx].Value);
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if (!pdv)
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continue;
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if (!LiveRegs[rx].Value) {
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setLiveReg(rx, pdv);
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continue;
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}
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// We have a live DomainValue from more than one predecessor.
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if (LiveRegs[rx].Value->isCollapsed()) {
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// We are already collapsed, but predecessor is not. Force it.
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unsigned Domain = LiveRegs[rx].Value->getFirstDomain();
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if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
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collapse(pdv, Domain);
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continue;
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}
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// Currently open, merge in predecessor.
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if (!pdv->isCollapsed())
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merge(LiveRegs[rx].Value, pdv);
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else
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force(rx, pdv->getFirstDomain());
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}
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}
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DEBUG(dbgs() << "BB#" << MBB->getNumber()
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<< (SeenUnknownBackEdge ? ": incomplete\n" : ": all preds known\n"));
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}
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void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
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assert(LiveRegs && "Must enter basic block first.");
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// Save live registers at end of MBB - used by enterBasicBlock().
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// Also use LiveOuts as a visited set to detect back-edges.
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bool First = LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second;
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if (First) {
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// LiveRegs was inserted in LiveOuts. Adjust all defs to be relative to
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// the end of this block instead of the beginning.
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for (unsigned i = 0, e = NumRegs; i != e; ++i)
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LiveRegs[i].Def -= CurInstr;
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} else {
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// Insertion failed, this must be the second pass.
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// Release all the DomainValues instead of keeping them.
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for (unsigned i = 0, e = NumRegs; i != e; ++i)
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release(LiveRegs[i].Value);
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delete[] LiveRegs;
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}
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LiveRegs = nullptr;
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}
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void ExeDepsFix::visitInstr(MachineInstr *MI) {
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if (MI->isDebugValue())
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return;
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// Update instructions with explicit execution domains.
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std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI);
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if (DomP.first) {
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if (DomP.second)
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visitSoftInstr(MI, DomP.second);
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else
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visitHardInstr(MI, DomP.first);
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}
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// Process defs to track register ages, and kill values clobbered by generic
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// instructions.
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processDefs(MI, !DomP.first);
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}
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/// \brief Return true to if it makes sense to break dependence on a partial def
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/// or undef use.
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bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
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unsigned Pref) {
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unsigned reg = MI->getOperand(OpIdx).getReg();
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for (int rx : regIndizes(reg)) {
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unsigned Clearance = CurInstr - LiveRegs[rx].Def;
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DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
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if (Pref > Clearance) {
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DEBUG(dbgs() << ": Break dependency.\n");
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continue;
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}
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// The current clearance seems OK, but we may be ignoring a def from a
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// back-edge.
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if (!SeenUnknownBackEdge || Pref <= unsigned(CurInstr)) {
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DEBUG(dbgs() << ": OK .\n");
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return false;
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}
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// A def from an unprocessed back-edge may make us break this dependency.
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DEBUG(dbgs() << ": Wait for back-edge to resolve.\n");
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return false;
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}
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return true;
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}
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// Update def-ages for registers defined by MI.
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// If Kill is set, also kill off DomainValues clobbered by the defs.
|
|
//
|
|
// Also break dependencies on partial defs and undef uses.
|
|
void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
|
|
assert(!MI->isDebugValue() && "Won't process debug values");
|
|
|
|
// Break dependence on undef uses. Do this before updating LiveRegs below.
|
|
unsigned OpNum;
|
|
unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI);
|
|
if (Pref) {
|
|
if (shouldBreakDependence(MI, OpNum, Pref))
|
|
UndefReads.push_back(std::make_pair(MI, OpNum));
|
|
}
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
for (unsigned i = 0,
|
|
e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
|
|
i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg())
|
|
continue;
|
|
if (MO.isImplicit())
|
|
break;
|
|
if (MO.isUse())
|
|
continue;
|
|
for (int rx : regIndizes(MO.getReg())) {
|
|
// This instruction explicitly defines rx.
|
|
DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
|
|
<< '\t' << *MI);
|
|
|
|
// Check clearance before partial register updates.
|
|
// Call breakDependence before setting LiveRegs[rx].Def.
|
|
unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI);
|
|
if (Pref && shouldBreakDependence(MI, i, Pref))
|
|
TII->breakPartialRegDependency(MI, i, TRI);
|
|
|
|
// How many instructions since rx was last written?
|
|
LiveRegs[rx].Def = CurInstr;
|
|
|
|
// Kill off domains redefined by generic instructions.
|
|
if (Kill)
|
|
kill(rx);
|
|
}
|
|
}
|
|
++CurInstr;
|
|
}
|
|
|
|
/// \break Break false dependencies on undefined register reads.
|
|
///
|
|
/// Walk the block backward computing precise liveness. This is expensive, so we
|
|
/// only do it on demand. Note that the occurrence of undefined register reads
|
|
/// that should be broken is very rare, but when they occur we may have many in
|
|
/// a single block.
|
|
void ExeDepsFix::processUndefReads(MachineBasicBlock *MBB) {
|
|
if (UndefReads.empty())
|
|
return;
|
|
|
|
// Collect this block's live out register units.
|
|
LiveRegSet.init(TRI);
|
|
LiveRegSet.addLiveOuts(MBB);
|
|
|
|
MachineInstr *UndefMI = UndefReads.back().first;
|
|
unsigned OpIdx = UndefReads.back().second;
|
|
|
|
for (MachineBasicBlock::reverse_iterator I = MBB->rbegin(), E = MBB->rend();
|
|
I != E; ++I) {
|
|
// Update liveness, including the current instruction's defs.
|
|
LiveRegSet.stepBackward(*I);
|
|
|
|
if (UndefMI == &*I) {
|
|
if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
|
|
TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
|
|
|
|
UndefReads.pop_back();
|
|
if (UndefReads.empty())
|
|
return;
|
|
|
|
UndefMI = UndefReads.back().first;
|
|
OpIdx = UndefReads.back().second;
|
|
}
|
|
}
|
|
}
|
|
|
|
// A hard instruction only works in one domain. All input registers will be
|
|
// forced into that domain.
|
|
void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
|
|
// Collapse all uses.
|
|
for (unsigned i = mi->getDesc().getNumDefs(),
|
|
e = mi->getDesc().getNumOperands(); i != e; ++i) {
|
|
MachineOperand &mo = mi->getOperand(i);
|
|
if (!mo.isReg()) continue;
|
|
for (int rx : regIndizes(mo.getReg())) {
|
|
force(rx, domain);
|
|
}
|
|
}
|
|
|
|
// Kill all defs and force them.
|
|
for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
|
|
MachineOperand &mo = mi->getOperand(i);
|
|
if (!mo.isReg()) continue;
|
|
for (int rx : regIndizes(mo.getReg())) {
|
|
kill(rx);
|
|
force(rx, domain);
|
|
}
|
|
}
|
|
}
|
|
|
|
// A soft instruction can be changed to work in other domains given by mask.
|
|
void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
|
|
// Bitmask of available domains for this instruction after taking collapsed
|
|
// operands into account.
|
|
unsigned available = mask;
|
|
|
|
// Scan the explicit use operands for incoming domains.
|
|
SmallVector<int, 4> used;
|
|
if (LiveRegs)
|
|
for (unsigned i = mi->getDesc().getNumDefs(),
|
|
e = mi->getDesc().getNumOperands(); i != e; ++i) {
|
|
MachineOperand &mo = mi->getOperand(i);
|
|
if (!mo.isReg()) continue;
|
|
for (int rx : regIndizes(mo.getReg())) {
|
|
DomainValue *dv = LiveRegs[rx].Value;
|
|
if (dv == nullptr)
|
|
continue;
|
|
// Bitmask of domains that dv and available have in common.
|
|
unsigned common = dv->getCommonDomains(available);
|
|
// Is it possible to use this collapsed register for free?
|
|
if (dv->isCollapsed()) {
|
|
// Restrict available domains to the ones in common with the operand.
|
|
// If there are no common domains, we must pay the cross-domain
|
|
// penalty for this operand.
|
|
if (common) available = common;
|
|
} else if (common)
|
|
// Open DomainValue is compatible, save it for merging.
|
|
used.push_back(rx);
|
|
else
|
|
// Open DomainValue is not compatible with instruction. It is useless
|
|
// now.
|
|
kill(rx);
|
|
}
|
|
}
|
|
|
|
// If the collapsed operands force a single domain, propagate the collapse.
|
|
if (isPowerOf2_32(available)) {
|
|
unsigned domain = countTrailingZeros(available);
|
|
TII->setExecutionDomain(mi, domain);
|
|
visitHardInstr(mi, domain);
|
|
return;
|
|
}
|
|
|
|
// Kill off any remaining uses that don't match available, and build a list of
|
|
// incoming DomainValues that we want to merge.
|
|
SmallVector<LiveReg, 4> Regs;
|
|
for (SmallVectorImpl<int>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
|
|
int rx = *i;
|
|
assert(LiveRegs && "no space allocated for live registers");
|
|
const LiveReg &LR = LiveRegs[rx];
|
|
// This useless DomainValue could have been missed above.
|
|
if (!LR.Value->getCommonDomains(available)) {
|
|
kill(rx);
|
|
continue;
|
|
}
|
|
// Sorted insertion.
|
|
bool Inserted = false;
|
|
for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
|
|
i != e && !Inserted; ++i) {
|
|
if (LR.Def < i->Def) {
|
|
Inserted = true;
|
|
Regs.insert(i, LR);
|
|
}
|
|
}
|
|
if (!Inserted)
|
|
Regs.push_back(LR);
|
|
}
|
|
|
|
// doms are now sorted in order of appearance. Try to merge them all, giving
|
|
// priority to the latest ones.
|
|
DomainValue *dv = nullptr;
|
|
while (!Regs.empty()) {
|
|
if (!dv) {
|
|
dv = Regs.pop_back_val().Value;
|
|
// Force the first dv to match the current instruction.
|
|
dv->AvailableDomains = dv->getCommonDomains(available);
|
|
assert(dv->AvailableDomains && "Domain should have been filtered");
|
|
continue;
|
|
}
|
|
|
|
DomainValue *Latest = Regs.pop_back_val().Value;
|
|
// Skip already merged values.
|
|
if (Latest == dv || Latest->Next)
|
|
continue;
|
|
if (merge(dv, Latest))
|
|
continue;
|
|
|
|
// If latest didn't merge, it is useless now. Kill all registers using it.
|
|
for (int i : used) {
|
|
assert(LiveRegs && "no space allocated for live registers");
|
|
if (LiveRegs[i].Value == Latest)
|
|
kill(i);
|
|
}
|
|
}
|
|
|
|
// dv is the DomainValue we are going to use for this instruction.
|
|
if (!dv) {
|
|
dv = alloc();
|
|
dv->AvailableDomains = available;
|
|
}
|
|
dv->Instrs.push_back(mi);
|
|
|
|
// Finally set all defs and non-collapsed uses to dv. We must iterate through
|
|
// all the operators, including imp-def ones.
|
|
for (MachineInstr::mop_iterator ii = mi->operands_begin(),
|
|
ee = mi->operands_end();
|
|
ii != ee; ++ii) {
|
|
MachineOperand &mo = *ii;
|
|
if (!mo.isReg()) continue;
|
|
for (int rx : regIndizes(mo.getReg())) {
|
|
if (!LiveRegs[rx].Value || (mo.isDef() && LiveRegs[rx].Value != dv)) {
|
|
kill(rx);
|
|
setLiveReg(rx, dv);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
|
|
MF = &mf;
|
|
TII = MF->getSubtarget().getInstrInfo();
|
|
TRI = MF->getSubtarget().getRegisterInfo();
|
|
LiveRegs = nullptr;
|
|
assert(NumRegs == RC->getNumRegs() && "Bad regclass");
|
|
|
|
DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: "
|
|
<< TRI->getRegClassName(RC) << " **********\n");
|
|
|
|
// If no relevant registers are used in the function, we can skip it
|
|
// completely.
|
|
bool anyregs = false;
|
|
for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
|
|
I != E; ++I)
|
|
if (MF->getRegInfo().isPhysRegUsed(*I)) {
|
|
anyregs = true;
|
|
break;
|
|
}
|
|
if (!anyregs) return false;
|
|
|
|
// Initialize the AliasMap on the first use.
|
|
if (AliasMap.empty()) {
|
|
// Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and
|
|
// therefore the LiveRegs array.
|
|
AliasMap.resize(TRI->getNumRegs());
|
|
for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
|
|
for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true);
|
|
AI.isValid(); ++AI)
|
|
AliasMap[*AI].push_back(i);
|
|
}
|
|
|
|
MachineBasicBlock *Entry = MF->begin();
|
|
ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
|
|
SmallVector<MachineBasicBlock*, 16> Loops;
|
|
for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
|
|
MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
|
|
MachineBasicBlock *MBB = *MBBI;
|
|
enterBasicBlock(MBB);
|
|
if (SeenUnknownBackEdge)
|
|
Loops.push_back(MBB);
|
|
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
|
|
++I)
|
|
visitInstr(I);
|
|
processUndefReads(MBB);
|
|
leaveBasicBlock(MBB);
|
|
}
|
|
|
|
// Visit all the loop blocks again in order to merge DomainValues from
|
|
// back-edges.
|
|
for (unsigned i = 0, e = Loops.size(); i != e; ++i) {
|
|
MachineBasicBlock *MBB = Loops[i];
|
|
enterBasicBlock(MBB);
|
|
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
|
|
++I)
|
|
if (!I->isDebugValue())
|
|
processDefs(I, false);
|
|
processUndefReads(MBB);
|
|
leaveBasicBlock(MBB);
|
|
}
|
|
|
|
// Clear the LiveOuts vectors and collapse any remaining DomainValues.
|
|
for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
|
|
MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
|
|
LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI);
|
|
if (FI == LiveOuts.end() || !FI->second)
|
|
continue;
|
|
for (unsigned i = 0, e = NumRegs; i != e; ++i)
|
|
if (FI->second[i].Value)
|
|
release(FI->second[i].Value);
|
|
delete[] FI->second;
|
|
}
|
|
LiveOuts.clear();
|
|
UndefReads.clear();
|
|
Avail.clear();
|
|
Allocator.DestroyAll();
|
|
|
|
return false;
|
|
}
|
|
|
|
FunctionPass *
|
|
llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) {
|
|
return new ExeDepsFix(RC);
|
|
}
|