mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
125 lines
5.1 KiB
LLVM
125 lines
5.1 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vtrni8:
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;CHECK: vtrn.8
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;CHECK-NEXT: vadd.i8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vtrni16:
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;CHECK: vtrn.16
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;CHECK-NEXT: vadd.i16
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = add <4 x i16> %tmp3, %tmp4
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ret <4 x i16> %tmp5
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}
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define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vtrni32:
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;CHECK: vtrn.32
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;CHECK-NEXT: vadd.i32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
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%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
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%tmp5 = add <2 x i32> %tmp3, %tmp4
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ret <2 x i32> %tmp5
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}
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define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vtrnf:
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;CHECK: vtrn.32
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;CHECK-NEXT: vadd.f32
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
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%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
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%tmp5 = fadd <2 x float> %tmp3, %tmp4
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ret <2 x float> %tmp5
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}
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define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vtrnQi8:
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;CHECK: vtrn.8
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;CHECK-NEXT: vadd.i8
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = load <16 x i8>, <16 x i8>* %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
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%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
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%tmp5 = add <16 x i8> %tmp3, %tmp4
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ret <16 x i8> %tmp5
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}
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define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vtrnQi16:
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;CHECK: vtrn.16
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;CHECK-NEXT: vadd.i16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vtrnQi32:
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;CHECK: vtrn.32
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;CHECK-NEXT: vadd.i32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = load <4 x i32>, <4 x i32>* %B
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = add <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vtrnQf:
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;CHECK: vtrn.32
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;CHECK-NEXT: vadd.f32
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = fadd <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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; Undef shuffle indices should not prevent matching to VTRN:
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define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vtrni8_undef:
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;CHECK: vtrn.8
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;CHECK-NEXT: vadd.i8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vtrnQi16_undef:
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;CHECK: vtrn.16
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;CHECK-NEXT: vadd.i16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = load <8 x i16>, <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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