mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e4c88dd909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202599 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
3.6 KiB
C++
138 lines
3.6 KiB
C++
//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an Sparc MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "SparcInstPrinter.h"
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#include "Sparc.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
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// namespace. But SPARC backend uses "SP" as its namespace.
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namespace llvm {
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namespace Sparc {
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using namespace SP;
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}
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}
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#define GET_INSTRUCTION_NAME
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#define PRINT_ALIAS_INSTR
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#include "SparcGenAsmWriter.inc"
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void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
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{
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OS << '%' << StringRef(getRegisterName(RegNo)).lower();
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}
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void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot)
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{
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if (!printAliasInstr(MI, O) && !printSparcAliasInstr(MI, O))
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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}
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bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O)
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{
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switch (MI->getOpcode()) {
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default: return false;
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case SP::JMPLrr:
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case SP::JMPLri: {
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if (MI->getNumOperands() != 3)
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return false;
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if (!MI->getOperand(0).isReg())
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return false;
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switch (MI->getOperand(0).getReg()) {
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default: return false;
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case SP::G0: // jmp $addr
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O << "\tjmp "; printMemOperand(MI, 1, O);
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return true;
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case SP::O7: // call $addr
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O << "\tcall "; printMemOperand(MI, 1, O);
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return true;
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}
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}
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}
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}
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void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
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raw_ostream &O)
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{
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const MCOperand &MO = MI->getOperand (opNum);
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if (MO.isReg()) {
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printRegName(O, MO.getReg());
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return ;
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}
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if (MO.isImm()) {
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O << (int)MO.getImm();
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return;
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}
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assert(MO.isExpr() && "Unknown operand kind in printOperand");
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MO.getExpr()->print(O);
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}
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void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
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raw_ostream &O, const char *Modifier)
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{
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printOperand(MI, opNum, O);
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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O << ", ";
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printOperand(MI, opNum+1, O);
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return;
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}
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const MCOperand &MO = MI->getOperand(opNum+1);
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if (MO.isReg() && MO.getReg() == SP::G0)
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return; // don't print "+%g0"
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if (MO.isImm() && MO.getImm() == 0)
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return; // don't print "+0"
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O << "+";
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printOperand(MI, opNum+1, O);
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}
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void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
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raw_ostream &O)
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{
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int CC = (int)MI->getOperand(opNum).getImm();
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switch (MI->getOpcode()) {
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default: break;
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case SP::FBCOND:
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case SP::FBCONDA:
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case SP::MOVFCCrr:
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case SP::MOVFCCri:
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case SP::FMOVS_FCC:
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case SP::FMOVD_FCC:
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case SP::FMOVQ_FCC: // Make sure CC is a fp conditional flag.
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CC = (CC < 16) ? (CC + 16) : CC;
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break;
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}
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O << SPARCCondCodeToString((SPCC::CondCodes)CC);
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}
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bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
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raw_ostream &O)
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{
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assert(0 && "FIXME: Implement SparcInstPrinter::printGetPCX.");
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return true;
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}
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