Jozef Kolek e4e84b22fe [mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2. ... Differential Revision: http://reviews.llvm.org/D5800 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222352 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-19 13:23:58 +00:00
..
AArch64	[AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArch64 backend.	2014-11-19 06:39:53 +00:00
ARM	Fix ARM triple parsing	2014-11-17 14:08:57 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.	2014-11-19 13:23:58 +00:00
MSP430
NVPTX
PowerPC
R600	R600/SI: Implement areMemAccessesTriviallyDisjoint	2014-11-19 00:01:31 +00:00
SPARC
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	[Thumb1] Re-write emitThumbRegPlusImmediate	2014-11-17 11:18:10 +00:00
Thumb2
X86	[X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2	2014-11-19 10:06:49 +00:00
XCore