mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
2.9 KiB
LLVM
95 lines
2.9 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -verify-arm-pseudo-expand
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; <rdar://problem/8529919>
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%struct.foo = type { i32, i32 }
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define void @func() nounwind {
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entry:
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%tmp = load i32, i32* undef, align 4
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br label %bb1
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bb1:
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%tmp1 = and i32 %tmp, 16
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%tmp2 = icmp eq i32 %tmp1, 0
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%invok.1.i = select i1 %tmp2, i32 undef, i32 0
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%tmp119 = add i32 %invok.1.i, 0
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br i1 undef, label %bb2, label %exit
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bb2:
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%tmp120 = add i32 %tmp119, 0
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%scevgep810.i = getelementptr %struct.foo, %struct.foo* null, i32 %tmp120, i32 1
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store i32 undef, i32* %scevgep810.i, align 4
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br i1 undef, label %bb2, label %bb3
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bb3:
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br i1 %tmp2, label %bb2, label %bb2
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exit:
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ret void
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}
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; PR10520 - REG_SEQUENCE with implicit-def operands.
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define arm_aapcs_vfpcc void @foo() nounwind align 2 {
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bb:
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%tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> <i32 1>
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%tmp8 = bitcast <1 x i64> %tmp to <2 x float>
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%tmp9 = shufflevector <2 x float> %tmp8, <2 x float> %tmp8, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%tmp10 = fmul <4 x float> undef, %tmp9
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%tmp11 = fadd <4 x float> %tmp10, undef
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%tmp12 = fadd <4 x float> undef, %tmp11
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%tmp13 = bitcast <4 x float> %tmp12 to i128
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%tmp14 = bitcast i128 %tmp13 to <4 x float>
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%tmp15 = bitcast <4 x float> %tmp14 to i128
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%tmp16 = bitcast i128 %tmp15 to <4 x float>
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%tmp17 = bitcast <4 x float> %tmp16 to i128
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%tmp18 = bitcast i128 %tmp17 to <4 x float>
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%tmp19 = bitcast <4 x float> %tmp18 to i128
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%tmp20 = bitcast i128 %tmp19 to <4 x float>
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store <4 x float> %tmp20, <4 x float>* undef, align 16
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ret void
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}
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; PR10520, second bug. NEONMoveFixPass needs to preserve implicit operands.
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define arm_aapcs_vfpcc void @pr10520_2() nounwind align 2 {
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bb:
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%tmp76 = shufflevector <2 x i64> zeroinitializer, <2 x i64> zeroinitializer, <1 x i32> <i32 1>
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%tmp77 = bitcast <1 x i64> %tmp76 to <2 x float>
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%tmp78 = shufflevector <2 x float> %tmp77, <2 x float> %tmp77, <4 x i32> zeroinitializer
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%tmp81 = fmul <4 x float> undef, %tmp78
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%tmp82 = fadd <4 x float> %tmp81, undef
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%tmp85 = fadd <4 x float> %tmp82, undef
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%tmp86 = bitcast <4 x float> %tmp85 to i128
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%tmp136 = bitcast i128 %tmp86 to <4 x float>
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%tmp137 = bitcast <4 x float> %tmp136 to i128
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%tmp138 = bitcast i128 %tmp137 to <4 x float>
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%tmp139 = bitcast <4 x float> %tmp138 to i128
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%tmp152 = bitcast i128 %tmp139 to <4 x float>
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%tmp153 = bitcast <4 x float> %tmp152 to i128
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%tmp154 = bitcast i128 %tmp153 to <4 x float>
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store <4 x float> %tmp154, <4 x float>* undef, align 16
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ret void
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}
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; <rdar://problem/12721258>
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%A = type { %B }
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%B = type { i32 }
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define void @_Z3Foov() ssp {
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entry:
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br i1 true, label %exit, label %false
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false:
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invoke void undef(%A* undef)
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to label %exit unwind label %lpad
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lpad:
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%0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*)
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catch i8* null
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unreachable
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exit:
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ret void
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}
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declare i32 @__gxx_personality_sj0(...)
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