mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
fd481d05be
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209877 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
542 B
LLVM
15 lines
542 B
LLVM
; RUN: llc -march=arm64 < %s
|
|
|
|
; The DAGCombiner tries to do following shrink:
|
|
; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
|
|
; But currently it can't handle vector type and will trigger an assertion failure
|
|
; when it tries to generate an add mixed using vector type and scaler type.
|
|
; This test checks that such assertion failur should not happen.
|
|
define <1 x i64> @dotest(<1 x i64> %in0) {
|
|
entry:
|
|
%0 = add <1 x i64> %in0, %in0
|
|
%vshl_n = shl <1 x i64> %0, <i64 32>
|
|
%vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
|
|
ret <1 x i64> %vsra_n
|
|
}
|