mirror of
https://github.com/c64scene-ar/llvm-6502.git
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bd3327654b
disassembler API. Hooked this up to the ARM target so such tools as Darwin's otool(1) can now print things like branch targets for example this: blx _puts instead of this: blx #-36 And even print the expression encoded in the Mach-O relocation entried for things like this: movt r0, :upper16:((_foo-_bar)+1234) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129284 91177308-0d34-0410-b5e6-96231b3b80d8
590 lines
19 KiB
C++
590 lines
19 KiB
C++
//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the ARM Disassembler.
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// It contains code to implement the public interfaces of ARMDisassembler and
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// ThumbDisassembler, both of which are instances of MCDisassembler.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-disassembler"
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#include "ARMDisassembler.h"
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#include "ARMDisassemblerCore.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/MC/EDInstInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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//#define DEBUG(X) do { X; } while (0)
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/// ARMGenDecoderTables.inc - ARMDecoderTables.inc is tblgen'ed from
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/// ARMDecoderEmitter.cpp TableGen backend. It contains:
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///
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/// o Mappings from opcode to ARM/Thumb instruction format
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///
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/// o static uint16_t decodeInstruction(uint32_t insn) - the decoding function
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/// for an ARM instruction.
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///
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/// o static uint16_t decodeThumbInstruction(field_t insn) - the decoding
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/// function for a Thumb instruction.
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///
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#include "ARMGenDecoderTables.inc"
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#include "ARMGenEDInfo.inc"
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using namespace llvm;
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/// showBitVector - Use the raw_ostream to log a diagnostic message describing
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/// the inidividual bits of the instruction.
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///
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static inline void showBitVector(raw_ostream &os, const uint32_t &insn) {
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// Split the bit position markers into more than one lines to fit 80 columns.
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os << " 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11"
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<< " 10 9 8 7 6 5 4 3 2 1 0 \n";
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os << "---------------------------------------------------------------"
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<< "----------------------------------\n";
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os << '|';
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for (unsigned i = 32; i != 0; --i) {
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if (insn >> (i - 1) & 0x01)
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os << " 1";
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else
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os << " 0";
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os << (i%4 == 1 ? '|' : ':');
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}
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os << '\n';
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// Split the bit position markers into more than one lines to fit 80 columns.
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os << "---------------------------------------------------------------"
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<< "----------------------------------\n";
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os << '\n';
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}
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/// decodeARMInstruction is a decorator function which tries special cases of
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/// instruction matching before calling the auto-generated decoder function.
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static unsigned decodeARMInstruction(uint32_t &insn) {
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if (slice(insn, 31, 28) == 15)
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goto AutoGenedDecoder;
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// Special case processing, if any, goes here....
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// LLVM combines the offset mode of A8.6.197 & A8.6.198 into STRB.
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// The insufficient encoding information of the combined instruction confuses
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// the decoder wrt BFC/BFI. Therefore, we try to recover here.
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// For BFC, Inst{27-21} = 0b0111110 & Inst{6-0} = 0b0011111.
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// For BFI, Inst{27-21} = 0b0111110 & Inst{6-4} = 0b001 & Inst{3-0} =! 0b1111.
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if (slice(insn, 27, 21) == 0x3e && slice(insn, 6, 4) == 1) {
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if (slice(insn, 3, 0) == 15)
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return ARM::BFC;
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else
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return ARM::BFI;
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}
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// Ditto for STRBT, which is a super-instruction for A8.6.199 Encodings
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// A1 & A2.
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// As a result, the decoder fails to deocode USAT properly.
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if (slice(insn, 27, 21) == 0x37 && slice(insn, 5, 4) == 1)
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return ARM::USAT;
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// As a result, the decoder fails to deocode UQADD16 properly.
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if (slice(insn, 27, 20) == 0x66 && slice(insn, 7, 4) == 1)
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return ARM::UQADD16;
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// Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8.
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// As a result, the decoder fails to decode UMULL properly.
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if (slice(insn, 27, 21) == 0x04 && slice(insn, 7, 4) == 9) {
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return ARM::UMULL;
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}
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// Ditto for STR_PRE, which is a super-instruction for A8.6.194 & A8.6.195.
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// As a result, the decoder fails to decode SBFX properly.
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if (slice(insn, 27, 21) == 0x3d && slice(insn, 6, 4) == 5)
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return ARM::SBFX;
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// And STRB_PRE, which is a super-instruction for A8.6.197 & A8.6.198.
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// As a result, the decoder fails to decode UBFX properly.
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if (slice(insn, 27, 21) == 0x3f && slice(insn, 6, 4) == 5)
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return ARM::UBFX;
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// Ditto for STRT, which is a super-instruction for A8.6.210 Encoding A1 & A2.
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// As a result, the decoder fails to deocode SSAT properly.
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if (slice(insn, 27, 21) == 0x35 && slice(insn, 5, 4) == 1)
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return ARM::SSAT;
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// Ditto for RSCrs, which is a super-instruction for A8.6.146 & A8.6.147.
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// As a result, the decoder fails to decode STRHT/LDRHT/LDRSHT/LDRSBT.
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if (slice(insn, 27, 24) == 0) {
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switch (slice(insn, 21, 20)) {
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case 2:
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switch (slice(insn, 7, 4)) {
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case 11:
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return ARM::STRHT;
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default:
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break; // fallthrough
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}
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break;
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case 3:
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switch (slice(insn, 7, 4)) {
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case 11:
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return ARM::LDRHT;
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case 13:
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return ARM::LDRSBT;
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case 15:
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return ARM::LDRSHT;
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default:
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break; // fallthrough
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}
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break;
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default:
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break; // fallthrough
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}
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}
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// Ditto for SBCrs, which is a super-instruction for A8.6.152 & A8.6.153.
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// As a result, the decoder fails to decode STRH_Post/LDRD_POST/STRD_POST
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// properly.
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if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 0) {
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unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
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switch (slice(insn, 7, 4)) {
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case 11:
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switch (PW) {
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case 2: // Offset
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return ARM::STRH;
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case 3: // Pre-indexed
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return ARM::STRH_PRE;
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case 0: // Post-indexed
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return ARM::STRH_POST;
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default:
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break; // fallthrough
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}
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break;
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case 13:
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switch (PW) {
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case 2: // Offset
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return ARM::LDRD;
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case 3: // Pre-indexed
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return ARM::LDRD_PRE;
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case 0: // Post-indexed
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return ARM::LDRD_POST;
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default:
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break; // fallthrough
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}
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break;
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case 15:
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switch (PW) {
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case 2: // Offset
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return ARM::STRD;
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case 3: // Pre-indexed
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return ARM::STRD_PRE;
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case 0: // Post-indexed
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return ARM::STRD_POST;
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default:
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break; // fallthrough
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}
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break;
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default:
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break; // fallthrough
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}
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}
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// Ditto for SBCSSrs, which is a super-instruction for A8.6.152 & A8.6.153.
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// As a result, the decoder fails to decode LDRH_POST/LDRSB_POST/LDRSH_POST
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// properly.
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if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 1) {
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unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
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switch (slice(insn, 7, 4)) {
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case 11:
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switch (PW) {
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case 2: // Offset
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return ARM::LDRH;
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case 3: // Pre-indexed
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return ARM::LDRH_PRE;
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case 0: // Post-indexed
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return ARM::LDRH_POST;
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default:
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break; // fallthrough
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}
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break;
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case 13:
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switch (PW) {
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case 2: // Offset
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return ARM::LDRSB;
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case 3: // Pre-indexed
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return ARM::LDRSB_PRE;
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case 0: // Post-indexed
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return ARM::LDRSB_POST;
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default:
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break; // fallthrough
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}
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break;
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case 15:
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switch (PW) {
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case 2: // Offset
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return ARM::LDRSH;
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case 3: // Pre-indexed
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return ARM::LDRSH_PRE;
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case 0: // Post-indexed
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return ARM::LDRSH_POST;
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default:
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break; // fallthrough
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}
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break;
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default:
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break; // fallthrough
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}
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}
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AutoGenedDecoder:
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// Calling the auto-generated decoder function.
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return decodeInstruction(insn);
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}
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// Helper function for special case handling of LDR (literal) and friends.
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// See, for example, A6.3.7 Load word: Table A6-18 Load word.
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// See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
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// before returning it.
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static unsigned T2Morph2LoadLiteral(unsigned Opcode) {
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switch (Opcode) {
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default:
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return Opcode; // Return unmorphed opcode.
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case ARM::t2LDR_POST: case ARM::t2LDR_PRE:
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case ARM::t2LDRi12: case ARM::t2LDRi8:
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case ARM::t2LDRs: case ARM::t2LDRT:
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return ARM::t2LDRpci;
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case ARM::t2LDRB_POST: case ARM::t2LDRB_PRE:
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case ARM::t2LDRBi12: case ARM::t2LDRBi8:
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case ARM::t2LDRBs: case ARM::t2LDRBT:
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return ARM::t2LDRBpci;
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case ARM::t2LDRH_POST: case ARM::t2LDRH_PRE:
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case ARM::t2LDRHi12: case ARM::t2LDRHi8:
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case ARM::t2LDRHs: case ARM::t2LDRHT:
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return ARM::t2LDRHpci;
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case ARM::t2LDRSB_POST: case ARM::t2LDRSB_PRE:
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case ARM::t2LDRSBi12: case ARM::t2LDRSBi8:
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case ARM::t2LDRSBs: case ARM::t2LDRSBT:
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return ARM::t2LDRSBpci;
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case ARM::t2LDRSH_POST: case ARM::t2LDRSH_PRE:
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case ARM::t2LDRSHi12: case ARM::t2LDRSHi8:
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case ARM::t2LDRSHs: case ARM::t2LDRSHT:
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return ARM::t2LDRSHpci;
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}
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}
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// Helper function for special case handling of PLD (literal) and friends.
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// See A8.6.117 T1 & T2 and friends for why we morphed the opcode
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// before returning it.
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static unsigned T2Morph2PLDLiteral(unsigned Opcode) {
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switch (Opcode) {
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default:
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return Opcode; // Return unmorphed opcode.
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case ARM::t2PLDi8: case ARM::t2PLDs:
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case ARM::t2PLDWi12: case ARM::t2PLDWi8:
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case ARM::t2PLDWs:
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return ARM::t2PLDi12;
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case ARM::t2PLIi8: case ARM::t2PLIs:
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return ARM::t2PLIi12;
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}
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}
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/// decodeThumbSideEffect is a decorator function which can potentially twiddle
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/// the instruction or morph the returned opcode under Thumb2.
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///
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/// First it checks whether the insn is a NEON or VFP instr; if true, bit
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/// twiddling could be performed on insn to turn it into an ARM NEON/VFP
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/// equivalent instruction and decodeInstruction is called with the transformed
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/// insn.
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///
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/// Next, there is special handling for Load byte/halfword/word instruction by
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/// checking whether Rn=0b1111 and call T2Morph2LoadLiteral() on the decoded
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/// Thumb2 instruction. See comments below for further details.
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///
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/// Finally, one last check is made to see whether the insn is a NEON/VFP and
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/// decodeInstruction(insn) is invoked on the original insn.
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///
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/// Otherwise, decodeThumbInstruction is called with the original insn.
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static unsigned decodeThumbSideEffect(bool IsThumb2, unsigned &insn) {
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if (IsThumb2) {
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uint16_t op1 = slice(insn, 28, 27);
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uint16_t op2 = slice(insn, 26, 20);
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// A6.3 32-bit Thumb instruction encoding
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// Table A6-9 32-bit Thumb instruction encoding
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// The coprocessor instructions of interest are transformed to their ARM
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// equivalents.
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// --------- Transform Begin Marker ---------
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if ((op1 == 1 || op1 == 3) && slice(op2, 6, 4) == 7) {
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// A7.4 Advanced SIMD data-processing instructions
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// U bit of Thumb corresponds to Inst{24} of ARM.
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uint16_t U = slice(op1, 1, 1);
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// Inst{28-24} of ARM = {1,0,0,1,U};
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uint16_t bits28_24 = 9 << 1 | U;
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DEBUG(showBitVector(errs(), insn));
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setSlice(insn, 28, 24, bits28_24);
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return decodeInstruction(insn);
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}
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if (op1 == 3 && slice(op2, 6, 4) == 1 && slice(op2, 0, 0) == 0) {
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// A7.7 Advanced SIMD element or structure load/store instructions
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// Inst{27-24} of Thumb = 0b1001
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// Inst{27-24} of ARM = 0b0100
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DEBUG(showBitVector(errs(), insn));
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setSlice(insn, 27, 24, 4);
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return decodeInstruction(insn);
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}
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// --------- Transform End Marker ---------
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unsigned unmorphed = decodeThumbInstruction(insn);
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// See, for example, A6.3.7 Load word: Table A6-18 Load word.
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// See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
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// before returning it to our caller.
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if (op1 == 3 && slice(op2, 6, 5) == 0 && slice(op2, 0, 0) == 1
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&& slice(insn, 19, 16) == 15) {
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unsigned morphed = T2Morph2LoadLiteral(unmorphed);
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if (morphed != unmorphed)
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return morphed;
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}
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// See, for example, A8.6.117 PLD,PLDW (immediate) T1 & T2, and friends for
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// why we morphed the opcode before returning it to our caller.
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if (slice(insn, 31, 25) == 0x7C && slice(insn, 15, 12) == 0xF
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&& slice(insn, 22, 22) == 0 && slice(insn, 20, 20) == 1
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&& slice(insn, 19, 16) == 15) {
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unsigned morphed = T2Morph2PLDLiteral(unmorphed);
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if (morphed != unmorphed)
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return morphed;
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}
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// One last check for NEON/VFP instructions.
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if ((op1 == 1 || op1 == 3) && slice(op2, 6, 6) == 1)
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return decodeInstruction(insn);
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// Fall through.
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}
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return decodeThumbInstruction(insn);
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}
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//
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// Public interface for the disassembler
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//
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bool ARMDisassembler::getInstruction(MCInst &MI,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &os) const {
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// The machine instruction.
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uint32_t insn;
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uint8_t bytes[4];
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// We want to read exactly 4 bytes of data.
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if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
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return false;
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// Encoded as a small-endian 32-bit word in the stream.
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insn = (bytes[3] << 24) |
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(bytes[2] << 16) |
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(bytes[1] << 8) |
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(bytes[0] << 0);
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unsigned Opcode = decodeARMInstruction(insn);
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ARMFormat Format = ARMFormats[Opcode];
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Size = 4;
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DEBUG({
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errs() << "\nOpcode=" << Opcode << " Name=" <<ARMUtils::OpcodeName(Opcode)
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<< " Format=" << stringForARMFormat(Format) << '(' << (int)Format
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<< ")\n";
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showBitVector(errs(), insn);
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});
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OwningPtr<ARMBasicMCBuilder> Builder(CreateMCBuilder(Opcode, Format));
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if (!Builder)
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return false;
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Builder->setupBuilderForSymbolicDisassembly(getLLVMOpInfoCallback(),
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getDisInfoBlock(), getMCContext(),
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Address);
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if (!Builder->Build(MI, insn))
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return false;
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return true;
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}
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bool ThumbDisassembler::getInstruction(MCInst &MI,
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uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &os) const {
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// The Thumb instruction stream is a sequence of halhwords.
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// This represents the first halfword as well as the machine instruction
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// passed to decodeThumbInstruction(). For 16-bit Thumb instruction, the top
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// halfword of insn is 0x00 0x00; otherwise, the first halfword is moved to
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// the top half followed by the second halfword.
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unsigned insn = 0;
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// Possible second halfword.
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uint16_t insn1 = 0;
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// A6.1 Thumb instruction set encoding
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//
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// If bits [15:11] of the halfword being decoded take any of the following
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// values, the halfword is the first halfword of a 32-bit instruction:
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// o 0b11101
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// o 0b11110
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// o 0b11111.
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//
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// Otherwise, the halfword is a 16-bit instruction.
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// Read 2 bytes of data first.
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uint8_t bytes[2];
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if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
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return false;
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// Encoded as a small-endian 16-bit halfword in the stream.
|
|
insn = (bytes[1] << 8) | bytes[0];
|
|
unsigned bits15_11 = slice(insn, 15, 11);
|
|
bool IsThumb2 = false;
|
|
|
|
// 32-bit instructions if the bits [15:11] of the halfword matches
|
|
// { 0b11101 /* 0x1D */, 0b11110 /* 0x1E */, ob11111 /* 0x1F */ }.
|
|
if (bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) {
|
|
IsThumb2 = true;
|
|
if (Region.readBytes(Address + 2, 2, (uint8_t*)bytes, NULL) == -1)
|
|
return false;
|
|
// Encoded as a small-endian 16-bit halfword in the stream.
|
|
insn1 = (bytes[1] << 8) | bytes[0];
|
|
insn = (insn << 16 | insn1);
|
|
}
|
|
|
|
// The insn could potentially be bit-twiddled in order to be decoded as an ARM
|
|
// NEON/VFP opcode. In such case, the modified insn is later disassembled as
|
|
// an ARM NEON/VFP instruction.
|
|
//
|
|
// This is a short term solution for lack of encoding bits specified for the
|
|
// Thumb2 NEON/VFP instructions. The long term solution could be adding some
|
|
// infrastructure to have each instruction support more than one encodings.
|
|
// Which encoding is used would be based on which subtarget the compiler/
|
|
// disassembler is working with at the time. This would allow the sharing of
|
|
// the NEON patterns between ARM and Thumb2, as well as potential greater
|
|
// sharing between the regular ARM instructions and the 32-bit wide Thumb2
|
|
// instructions as well.
|
|
unsigned Opcode = decodeThumbSideEffect(IsThumb2, insn);
|
|
|
|
ARMFormat Format = ARMFormats[Opcode];
|
|
Size = IsThumb2 ? 4 : 2;
|
|
|
|
DEBUG({
|
|
errs() << "Opcode=" << Opcode << " Name=" << ARMUtils::OpcodeName(Opcode)
|
|
<< " Format=" << stringForARMFormat(Format) << '(' << (int)Format
|
|
<< ")\n";
|
|
showBitVector(errs(), insn);
|
|
});
|
|
|
|
OwningPtr<ARMBasicMCBuilder> Builder(CreateMCBuilder(Opcode, Format));
|
|
if (!Builder)
|
|
return false;
|
|
|
|
Builder->SetSession(const_cast<Session *>(&SO));
|
|
|
|
Builder->setupBuilderForSymbolicDisassembly(getLLVMOpInfoCallback(),
|
|
getDisInfoBlock(), getMCContext(),
|
|
Address);
|
|
|
|
if (!Builder->Build(MI, insn))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
// A8.6.50
|
|
// Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
|
|
static unsigned short CountITSize(unsigned ITMask) {
|
|
// First count the trailing zeros of the IT mask.
|
|
unsigned TZ = CountTrailingZeros_32(ITMask);
|
|
if (TZ > 3) {
|
|
DEBUG(errs() << "Encoding error: IT Mask '0000'");
|
|
return 0;
|
|
}
|
|
return (4 - TZ);
|
|
}
|
|
|
|
/// Init ITState. Note that at least one bit is always 1 in mask.
|
|
bool Session::InitIT(unsigned short bits7_0) {
|
|
ITCounter = CountITSize(slice(bits7_0, 3, 0));
|
|
if (ITCounter == 0)
|
|
return false;
|
|
|
|
// A8.6.50 IT
|
|
unsigned short FirstCond = slice(bits7_0, 7, 4);
|
|
if (FirstCond == 0xF) {
|
|
DEBUG(errs() << "Encoding error: IT FirstCond '1111'");
|
|
return false;
|
|
}
|
|
if (FirstCond == 0xE && ITCounter != 1) {
|
|
DEBUG(errs() << "Encoding error: IT FirstCond '1110' && Mask != '1000'");
|
|
return false;
|
|
}
|
|
|
|
ITState = bits7_0;
|
|
|
|
return true;
|
|
}
|
|
|
|
/// Update ITState if necessary.
|
|
void Session::UpdateIT() {
|
|
assert(ITCounter);
|
|
--ITCounter;
|
|
if (ITCounter == 0)
|
|
ITState = 0;
|
|
else {
|
|
unsigned short NewITState4_0 = slice(ITState, 4, 0) << 1;
|
|
setSlice(ITState, 4, 0, NewITState4_0);
|
|
}
|
|
}
|
|
|
|
static MCDisassembler *createARMDisassembler(const Target &T) {
|
|
return new ARMDisassembler;
|
|
}
|
|
|
|
static MCDisassembler *createThumbDisassembler(const Target &T) {
|
|
return new ThumbDisassembler;
|
|
}
|
|
|
|
extern "C" void LLVMInitializeARMDisassembler() {
|
|
// Register the disassembler.
|
|
TargetRegistry::RegisterMCDisassembler(TheARMTarget,
|
|
createARMDisassembler);
|
|
TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
|
|
createThumbDisassembler);
|
|
}
|
|
|
|
EDInstInfo *ARMDisassembler::getEDInfo() const {
|
|
return instInfoARM;
|
|
}
|
|
|
|
EDInstInfo *ThumbDisassembler::getEDInfo() const {
|
|
return instInfoARM;
|
|
}
|