mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-27 15:29:51 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
800 lines
26 KiB
C++
800 lines
26 KiB
C++
//===----- ScheduleDAGFast.cpp - Fast poor list scheduler -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a fast scheduler.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "InstrEmitter.h"
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#include "ScheduleDAGSDNodes.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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STATISTIC(NumUnfolds, "Number of nodes unfolded");
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STATISTIC(NumDups, "Number of duplicated nodes");
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STATISTIC(NumPRCopies, "Number of physical copies");
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static RegisterScheduler
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fastDAGScheduler("fast", "Fast suboptimal list scheduling",
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createFastDAGScheduler);
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static RegisterScheduler
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linearizeDAGScheduler("linearize", "Linearize DAG, no scheduling",
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createDAGLinearizer);
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namespace {
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/// FastPriorityQueue - A degenerate priority queue that considers
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/// all nodes to have the same priority.
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///
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struct FastPriorityQueue {
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SmallVector<SUnit *, 16> Queue;
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bool empty() const { return Queue.empty(); }
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void push(SUnit *U) {
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Queue.push_back(U);
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}
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SUnit *pop() {
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if (empty()) return NULL;
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SUnit *V = Queue.back();
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Queue.pop_back();
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return V;
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}
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};
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//===----------------------------------------------------------------------===//
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/// ScheduleDAGFast - The actual "fast" list scheduler implementation.
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///
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class ScheduleDAGFast : public ScheduleDAGSDNodes {
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private:
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/// AvailableQueue - The priority queue to use for the available SUnits.
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FastPriorityQueue AvailableQueue;
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/// LiveRegDefs - A set of physical registers and their definition
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/// that are "live". These nodes must be scheduled before any other nodes that
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/// modifies the registers can be scheduled.
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unsigned NumLiveRegs;
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std::vector<SUnit*> LiveRegDefs;
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std::vector<unsigned> LiveRegCycles;
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public:
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ScheduleDAGFast(MachineFunction &mf)
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: ScheduleDAGSDNodes(mf) {}
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void Schedule();
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/// AddPred - adds a predecessor edge to SUnit SU.
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/// This returns true if this is a new predecessor.
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void AddPred(SUnit *SU, const SDep &D) {
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SU->addPred(D);
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}
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/// RemovePred - removes a predecessor edge from SUnit SU.
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/// This returns true if an edge was removed.
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void RemovePred(SUnit *SU, const SDep &D) {
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SU->removePred(D);
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}
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private:
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void ReleasePred(SUnit *SU, SDep *PredEdge);
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void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
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void ScheduleNodeBottomUp(SUnit*, unsigned);
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SUnit *CopyAndMoveSuccessors(SUnit*);
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void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
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const TargetRegisterClass*,
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const TargetRegisterClass*,
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SmallVectorImpl<SUnit*>&);
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bool DelayForLiveRegsBottomUp(SUnit*, SmallVectorImpl<unsigned>&);
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void ListScheduleBottomUp();
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/// forceUnitLatencies - The fast scheduler doesn't care about real latencies.
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bool forceUnitLatencies() const { return true; }
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};
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} // end anonymous namespace
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/// Schedule - Schedule the DAG using list scheduling.
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void ScheduleDAGFast::Schedule() {
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DEBUG(dbgs() << "********** List Scheduling **********\n");
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NumLiveRegs = 0;
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LiveRegDefs.resize(TRI->getNumRegs(), NULL);
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LiveRegCycles.resize(TRI->getNumRegs(), 0);
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// Build the scheduling graph.
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BuildSchedGraph(NULL);
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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// Execute the actual scheduling loop.
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ListScheduleBottomUp();
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}
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//===----------------------------------------------------------------------===//
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// Bottom-Up Scheduling
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//===----------------------------------------------------------------------===//
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
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void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
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SUnit *PredSU = PredEdge->getSUnit();
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#ifndef NDEBUG
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if (PredSU->NumSuccsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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PredSU->dump(this);
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dbgs() << " has been released too many times!\n";
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llvm_unreachable(0);
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}
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#endif
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--PredSU->NumSuccsLeft;
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// If all the node's successors are scheduled, this node is ready
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// to be scheduled. Ignore the special EntrySU node.
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if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
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PredSU->isAvailable = true;
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AvailableQueue.push(PredSU);
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}
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}
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void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) {
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// Bottom up: release predecessors
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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ReleasePred(SU, &*I);
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if (I->isAssignedRegDep()) {
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// This is a physical register dependency and it's impossible or
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// expensive to copy the register. Make sure nothing that can
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// clobber the register is scheduled between the predecessor and
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// this node.
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if (!LiveRegDefs[I->getReg()]) {
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++NumLiveRegs;
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LiveRegDefs[I->getReg()] = I->getSUnit();
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LiveRegCycles[I->getReg()] = CurCycle;
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}
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}
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}
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}
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/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
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/// count of its predecessors. If a predecessor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGFast::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
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DEBUG(SU->dump(this));
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assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!");
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SU->setHeightToAtLeast(CurCycle);
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Sequence.push_back(SU);
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ReleasePredecessors(SU, CurCycle);
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// Release all the implicit physical register defs that are live.
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isAssignedRegDep()) {
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if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
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assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
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assert(LiveRegDefs[I->getReg()] == SU &&
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"Physical register dependency violated?");
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--NumLiveRegs;
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LiveRegDefs[I->getReg()] = NULL;
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LiveRegCycles[I->getReg()] = 0;
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}
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}
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}
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SU->isScheduled = true;
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}
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/// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
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/// successors to the newly created node.
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SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) {
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if (SU->getNode()->getGluedNode())
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return NULL;
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SDNode *N = SU->getNode();
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if (!N)
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return NULL;
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SUnit *NewSU;
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bool TryUnfold = false;
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for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
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EVT VT = N->getValueType(i);
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if (VT == MVT::Glue)
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return NULL;
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else if (VT == MVT::Other)
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TryUnfold = true;
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}
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
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const SDValue &Op = N->getOperand(i);
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EVT VT = Op.getNode()->getValueType(Op.getResNo());
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if (VT == MVT::Glue)
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return NULL;
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}
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if (TryUnfold) {
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SmallVector<SDNode*, 2> NewNodes;
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if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
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return NULL;
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DEBUG(dbgs() << "Unfolding SU # " << SU->NodeNum << "\n");
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assert(NewNodes.size() == 2 && "Expected a load folding node!");
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N = NewNodes[1];
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SDNode *LoadNode = NewNodes[0];
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unsigned NumVals = N->getNumValues();
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unsigned OldNumVals = SU->getNode()->getNumValues();
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for (unsigned i = 0; i != NumVals; ++i)
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DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
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DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
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SDValue(LoadNode, 1));
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SUnit *NewSU = newSUnit(N);
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assert(N->getNodeId() == -1 && "Node already inserted!");
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N->setNodeId(NewSU->NodeNum);
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const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
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for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
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if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
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NewSU->isTwoAddress = true;
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break;
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}
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}
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if (MCID.isCommutable())
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NewSU->isCommutable = true;
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// LoadNode may already exist. This can happen when there is another
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// load from the same location and producing the same type of value
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// but it has different alignment or volatileness.
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bool isNewLoad = true;
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SUnit *LoadSU;
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if (LoadNode->getNodeId() != -1) {
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LoadSU = &SUnits[LoadNode->getNodeId()];
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isNewLoad = false;
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} else {
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LoadSU = newSUnit(LoadNode);
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LoadNode->setNodeId(LoadSU->NodeNum);
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}
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SDep ChainPred;
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SmallVector<SDep, 4> ChainSuccs;
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SmallVector<SDep, 4> LoadPreds;
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SmallVector<SDep, 4> NodePreds;
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SmallVector<SDep, 4> NodeSuccs;
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (I->isCtrl())
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ChainPred = *I;
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else if (I->getSUnit()->getNode() &&
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I->getSUnit()->getNode()->isOperandOf(LoadNode))
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LoadPreds.push_back(*I);
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else
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NodePreds.push_back(*I);
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}
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isCtrl())
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ChainSuccs.push_back(*I);
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else
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NodeSuccs.push_back(*I);
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}
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if (ChainPred.getSUnit()) {
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RemovePred(SU, ChainPred);
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if (isNewLoad)
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AddPred(LoadSU, ChainPred);
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}
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for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
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const SDep &Pred = LoadPreds[i];
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RemovePred(SU, Pred);
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if (isNewLoad) {
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AddPred(LoadSU, Pred);
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}
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}
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for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
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const SDep &Pred = NodePreds[i];
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RemovePred(SU, Pred);
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AddPred(NewSU, Pred);
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}
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for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
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SDep D = NodeSuccs[i];
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SUnit *SuccDep = D.getSUnit();
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D.setSUnit(SU);
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RemovePred(SuccDep, D);
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D.setSUnit(NewSU);
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AddPred(SuccDep, D);
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}
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for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
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SDep D = ChainSuccs[i];
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SUnit *SuccDep = D.getSUnit();
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D.setSUnit(SU);
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RemovePred(SuccDep, D);
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if (isNewLoad) {
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D.setSUnit(LoadSU);
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AddPred(SuccDep, D);
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}
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}
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if (isNewLoad) {
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SDep D(LoadSU, SDep::Barrier);
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D.setLatency(LoadSU->Latency);
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AddPred(NewSU, D);
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}
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++NumUnfolds;
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if (NewSU->NumSuccsLeft == 0) {
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NewSU->isAvailable = true;
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return NewSU;
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}
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SU = NewSU;
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}
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DEBUG(dbgs() << "Duplicating SU # " << SU->NodeNum << "\n");
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NewSU = Clone(SU);
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// New SUnit has the exact same predecessors.
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I)
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if (!I->isArtificial())
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AddPred(NewSU, *I);
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// Only copy scheduled successors. Cut them from old node's successor
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// list and move them over.
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SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isArtificial())
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continue;
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SUnit *SuccSU = I->getSUnit();
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if (SuccSU->isScheduled) {
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SDep D = *I;
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D.setSUnit(NewSU);
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AddPred(SuccSU, D);
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D.setSUnit(SU);
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DelDeps.push_back(std::make_pair(SuccSU, D));
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}
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}
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for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
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RemovePred(DelDeps[i].first, DelDeps[i].second);
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++NumDups;
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return NewSU;
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}
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/// InsertCopiesAndMoveSuccs - Insert register copies and move all
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/// scheduled successors of the given SUnit to the last copy.
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void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC,
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SmallVectorImpl<SUnit*> &Copies) {
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SUnit *CopyFromSU = newSUnit(static_cast<SDNode *>(NULL));
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CopyFromSU->CopySrcRC = SrcRC;
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CopyFromSU->CopyDstRC = DestRC;
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SUnit *CopyToSU = newSUnit(static_cast<SDNode *>(NULL));
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CopyToSU->CopySrcRC = DestRC;
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CopyToSU->CopyDstRC = SrcRC;
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// Only copy scheduled successors. Cut them from old node's successor
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// list and move them over.
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SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I) {
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if (I->isArtificial())
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continue;
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SUnit *SuccSU = I->getSUnit();
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if (SuccSU->isScheduled) {
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SDep D = *I;
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D.setSUnit(CopyToSU);
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AddPred(SuccSU, D);
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DelDeps.push_back(std::make_pair(SuccSU, *I));
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}
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}
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for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
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RemovePred(DelDeps[i].first, DelDeps[i].second);
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}
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SDep FromDep(SU, SDep::Data, Reg);
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FromDep.setLatency(SU->Latency);
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AddPred(CopyFromSU, FromDep);
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SDep ToDep(CopyFromSU, SDep::Data, 0);
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ToDep.setLatency(CopyFromSU->Latency);
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AddPred(CopyToSU, ToDep);
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Copies.push_back(CopyFromSU);
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Copies.push_back(CopyToSU);
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++NumPRCopies;
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}
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/// getPhysicalRegisterVT - Returns the ValueType of the physical register
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/// definition of the specified node.
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/// FIXME: Move to SelectionDAG?
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static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
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const TargetInstrInfo *TII) {
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const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
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assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
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unsigned NumRes = MCID.getNumDefs();
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for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
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if (Reg == *ImpDef)
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break;
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++NumRes;
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}
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return N->getValueType(NumRes);
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}
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/// CheckForLiveRegDef - Return true and update live register vector if the
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/// specified register def of the specified SUnit clobbers any "live" registers.
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static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,
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std::vector<SUnit*> &LiveRegDefs,
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SmallSet<unsigned, 4> &RegAdded,
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SmallVectorImpl<unsigned> &LRegs,
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const TargetRegisterInfo *TRI) {
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bool Added = false;
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
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if (LiveRegDefs[*AI] && LiveRegDefs[*AI] != SU) {
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if (RegAdded.insert(*AI)) {
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LRegs.push_back(*AI);
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Added = true;
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}
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}
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}
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return Added;
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}
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/// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
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/// scheduling of the given node to satisfy live physical register dependencies.
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/// If the specific node is the last one that's available to schedule, do
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/// whatever is necessary (i.e. backtracking or cloning) to make it possible.
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bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
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SmallVectorImpl<unsigned> &LRegs){
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if (NumLiveRegs == 0)
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return false;
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SmallSet<unsigned, 4> RegAdded;
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// If this node would clobber any "live" register, then it's not ready.
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (I->isAssignedRegDep()) {
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|
CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
|
|
RegAdded, LRegs, TRI);
|
|
}
|
|
}
|
|
|
|
for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) {
|
|
if (Node->getOpcode() == ISD::INLINEASM) {
|
|
// Inline asm can clobber physical defs.
|
|
unsigned NumOps = Node->getNumOperands();
|
|
if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
|
|
--NumOps; // Ignore the glue operand.
|
|
|
|
for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
|
|
unsigned Flags =
|
|
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
|
|
unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
|
|
|
|
++i; // Skip the ID value.
|
|
if (InlineAsm::isRegDefKind(Flags) ||
|
|
InlineAsm::isRegDefEarlyClobberKind(Flags) ||
|
|
InlineAsm::isClobberKind(Flags)) {
|
|
// Check for def of register or earlyclobber register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
|
|
}
|
|
} else
|
|
i += NumVals;
|
|
}
|
|
continue;
|
|
}
|
|
if (!Node->isMachineOpcode())
|
|
continue;
|
|
const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
|
|
if (!MCID.ImplicitDefs)
|
|
continue;
|
|
for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
|
|
CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
|
|
}
|
|
}
|
|
return !LRegs.empty();
|
|
}
|
|
|
|
|
|
/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
|
|
/// schedulers.
|
|
void ScheduleDAGFast::ListScheduleBottomUp() {
|
|
unsigned CurCycle = 0;
|
|
|
|
// Release any predecessors of the special Exit node.
|
|
ReleasePredecessors(&ExitSU, CurCycle);
|
|
|
|
// Add root to Available queue.
|
|
if (!SUnits.empty()) {
|
|
SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
|
|
assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
|
|
RootSU->isAvailable = true;
|
|
AvailableQueue.push(RootSU);
|
|
}
|
|
|
|
// While Available queue is not empty, grab the node with the highest
|
|
// priority. If it is not ready put it back. Schedule the node.
|
|
SmallVector<SUnit*, 4> NotReady;
|
|
DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
|
|
Sequence.reserve(SUnits.size());
|
|
while (!AvailableQueue.empty()) {
|
|
bool Delayed = false;
|
|
LRegsMap.clear();
|
|
SUnit *CurSU = AvailableQueue.pop();
|
|
while (CurSU) {
|
|
SmallVector<unsigned, 4> LRegs;
|
|
if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
|
|
break;
|
|
Delayed = true;
|
|
LRegsMap.insert(std::make_pair(CurSU, LRegs));
|
|
|
|
CurSU->isPending = true; // This SU is not in AvailableQueue right now.
|
|
NotReady.push_back(CurSU);
|
|
CurSU = AvailableQueue.pop();
|
|
}
|
|
|
|
// All candidates are delayed due to live physical reg dependencies.
|
|
// Try code duplication or inserting cross class copies
|
|
// to resolve it.
|
|
if (Delayed && !CurSU) {
|
|
if (!CurSU) {
|
|
// Try duplicating the nodes that produces these
|
|
// "expensive to copy" values to break the dependency. In case even
|
|
// that doesn't work, insert cross class copies.
|
|
SUnit *TrySU = NotReady[0];
|
|
SmallVectorImpl<unsigned> &LRegs = LRegsMap[TrySU];
|
|
assert(LRegs.size() == 1 && "Can't handle this yet!");
|
|
unsigned Reg = LRegs[0];
|
|
SUnit *LRDef = LiveRegDefs[Reg];
|
|
EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
|
|
const TargetRegisterClass *RC =
|
|
TRI->getMinimalPhysRegClass(Reg, VT);
|
|
const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
|
|
|
|
// If cross copy register class is the same as RC, then it must be
|
|
// possible copy the value directly. Do not try duplicate the def.
|
|
// If cross copy register class is not the same as RC, then it's
|
|
// possible to copy the value but it require cross register class copies
|
|
// and it is expensive.
|
|
// If cross copy register class is null, then it's not possible to copy
|
|
// the value at all.
|
|
SUnit *NewDef = 0;
|
|
if (DestRC != RC) {
|
|
NewDef = CopyAndMoveSuccessors(LRDef);
|
|
if (!DestRC && !NewDef)
|
|
report_fatal_error("Can't handle live physical "
|
|
"register dependency!");
|
|
}
|
|
if (!NewDef) {
|
|
// Issue copies, these can be expensive cross register class copies.
|
|
SmallVector<SUnit*, 2> Copies;
|
|
InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
|
|
DEBUG(dbgs() << "Adding an edge from SU # " << TrySU->NodeNum
|
|
<< " to SU #" << Copies.front()->NodeNum << "\n");
|
|
AddPred(TrySU, SDep(Copies.front(), SDep::Artificial));
|
|
NewDef = Copies.back();
|
|
}
|
|
|
|
DEBUG(dbgs() << "Adding an edge from SU # " << NewDef->NodeNum
|
|
<< " to SU #" << TrySU->NodeNum << "\n");
|
|
LiveRegDefs[Reg] = NewDef;
|
|
AddPred(NewDef, SDep(TrySU, SDep::Artificial));
|
|
TrySU->isAvailable = false;
|
|
CurSU = NewDef;
|
|
}
|
|
|
|
if (!CurSU) {
|
|
llvm_unreachable("Unable to resolve live physical register dependencies!");
|
|
}
|
|
}
|
|
|
|
// Add the nodes that aren't ready back onto the available list.
|
|
for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
|
|
NotReady[i]->isPending = false;
|
|
// May no longer be available due to backtracking.
|
|
if (NotReady[i]->isAvailable)
|
|
AvailableQueue.push(NotReady[i]);
|
|
}
|
|
NotReady.clear();
|
|
|
|
if (CurSU)
|
|
ScheduleNodeBottomUp(CurSU, CurCycle);
|
|
++CurCycle;
|
|
}
|
|
|
|
// Reverse the order since it is bottom up.
|
|
std::reverse(Sequence.begin(), Sequence.end());
|
|
|
|
#ifndef NDEBUG
|
|
VerifyScheduledSequence(/*isBottomUp=*/true);
|
|
#endif
|
|
}
|
|
|
|
|
|
namespace {
|
|
//===----------------------------------------------------------------------===//
|
|
// ScheduleDAGLinearize - No scheduling scheduler, it simply linearize the
|
|
// DAG in topological order.
|
|
// IMPORTANT: this may not work for targets with phyreg dependency.
|
|
//
|
|
class ScheduleDAGLinearize : public ScheduleDAGSDNodes {
|
|
public:
|
|
ScheduleDAGLinearize(MachineFunction &mf) : ScheduleDAGSDNodes(mf) {}
|
|
|
|
void Schedule();
|
|
|
|
MachineBasicBlock *EmitSchedule(MachineBasicBlock::iterator &InsertPos);
|
|
|
|
private:
|
|
std::vector<SDNode*> Sequence;
|
|
DenseMap<SDNode*, SDNode*> GluedMap; // Cache glue to its user
|
|
|
|
void ScheduleNode(SDNode *N);
|
|
};
|
|
} // end anonymous namespace
|
|
|
|
void ScheduleDAGLinearize::ScheduleNode(SDNode *N) {
|
|
if (N->getNodeId() != 0)
|
|
llvm_unreachable(0);
|
|
|
|
if (!N->isMachineOpcode() &&
|
|
(N->getOpcode() == ISD::EntryToken || isPassiveNode(N)))
|
|
// These nodes do not need to be translated into MIs.
|
|
return;
|
|
|
|
DEBUG(dbgs() << "\n*** Scheduling: ");
|
|
DEBUG(N->dump(DAG));
|
|
Sequence.push_back(N);
|
|
|
|
unsigned NumOps = N->getNumOperands();
|
|
if (unsigned NumLeft = NumOps) {
|
|
SDNode *GluedOpN = 0;
|
|
do {
|
|
const SDValue &Op = N->getOperand(NumLeft-1);
|
|
SDNode *OpN = Op.getNode();
|
|
|
|
if (NumLeft == NumOps && Op.getValueType() == MVT::Glue) {
|
|
// Schedule glue operand right above N.
|
|
GluedOpN = OpN;
|
|
assert(OpN->getNodeId() != 0 && "Glue operand not ready?");
|
|
OpN->setNodeId(0);
|
|
ScheduleNode(OpN);
|
|
continue;
|
|
}
|
|
|
|
if (OpN == GluedOpN)
|
|
// Glue operand is already scheduled.
|
|
continue;
|
|
|
|
DenseMap<SDNode*, SDNode*>::iterator DI = GluedMap.find(OpN);
|
|
if (DI != GluedMap.end() && DI->second != N)
|
|
// Users of glues are counted against the glued users.
|
|
OpN = DI->second;
|
|
|
|
unsigned Degree = OpN->getNodeId();
|
|
assert(Degree > 0 && "Predecessor over-released!");
|
|
OpN->setNodeId(--Degree);
|
|
if (Degree == 0)
|
|
ScheduleNode(OpN);
|
|
} while (--NumLeft);
|
|
}
|
|
}
|
|
|
|
/// findGluedUser - Find the representative use of a glue value by walking
|
|
/// the use chain.
|
|
static SDNode *findGluedUser(SDNode *N) {
|
|
while (SDNode *Glued = N->getGluedUser())
|
|
N = Glued;
|
|
return N;
|
|
}
|
|
|
|
void ScheduleDAGLinearize::Schedule() {
|
|
DEBUG(dbgs() << "********** DAG Linearization **********\n");
|
|
|
|
SmallVector<SDNode*, 8> Glues;
|
|
unsigned DAGSize = 0;
|
|
for (SelectionDAG::allnodes_iterator I = DAG->allnodes_begin(),
|
|
E = DAG->allnodes_end(); I != E; ++I) {
|
|
SDNode *N = I;
|
|
|
|
// Use node id to record degree.
|
|
unsigned Degree = N->use_size();
|
|
N->setNodeId(Degree);
|
|
unsigned NumVals = N->getNumValues();
|
|
if (NumVals && N->getValueType(NumVals-1) == MVT::Glue &&
|
|
N->hasAnyUseOfValue(NumVals-1)) {
|
|
SDNode *User = findGluedUser(N);
|
|
if (User) {
|
|
Glues.push_back(N);
|
|
GluedMap.insert(std::make_pair(N, User));
|
|
}
|
|
}
|
|
|
|
if (N->isMachineOpcode() ||
|
|
(N->getOpcode() != ISD::EntryToken && !isPassiveNode(N)))
|
|
++DAGSize;
|
|
}
|
|
|
|
for (unsigned i = 0, e = Glues.size(); i != e; ++i) {
|
|
SDNode *Glue = Glues[i];
|
|
SDNode *GUser = GluedMap[Glue];
|
|
unsigned Degree = Glue->getNodeId();
|
|
unsigned UDegree = GUser->getNodeId();
|
|
|
|
// Glue user must be scheduled together with the glue operand. So other
|
|
// users of the glue operand must be treated as its users.
|
|
SDNode *ImmGUser = Glue->getGluedUser();
|
|
for (SDNode::use_iterator ui = Glue->use_begin(), ue = Glue->use_end();
|
|
ui != ue; ++ui)
|
|
if (*ui == ImmGUser)
|
|
--Degree;
|
|
GUser->setNodeId(UDegree + Degree);
|
|
Glue->setNodeId(1);
|
|
}
|
|
|
|
Sequence.reserve(DAGSize);
|
|
ScheduleNode(DAG->getRoot().getNode());
|
|
}
|
|
|
|
MachineBasicBlock*
|
|
ScheduleDAGLinearize::EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
|
|
InstrEmitter Emitter(BB, InsertPos);
|
|
DenseMap<SDValue, unsigned> VRBaseMap;
|
|
|
|
DEBUG({
|
|
dbgs() << "\n*** Final schedule ***\n";
|
|
});
|
|
|
|
// FIXME: Handle dbg_values.
|
|
unsigned NumNodes = Sequence.size();
|
|
for (unsigned i = 0; i != NumNodes; ++i) {
|
|
SDNode *N = Sequence[NumNodes-i-1];
|
|
DEBUG(N->dump(DAG));
|
|
Emitter.EmitNode(N, false, false, VRBaseMap);
|
|
}
|
|
|
|
DEBUG(dbgs() << '\n');
|
|
|
|
InsertPos = Emitter.getInsertPos();
|
|
return Emitter.getBlock();
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Public Constructor Functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
llvm::ScheduleDAGSDNodes *
|
|
llvm::createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
|
|
return new ScheduleDAGFast(*IS->MF);
|
|
}
|
|
|
|
llvm::ScheduleDAGSDNodes *
|
|
llvm::createDAGLinearizer(SelectionDAGISel *IS, CodeGenOpt::Level) {
|
|
return new ScheduleDAGLinearize(*IS->MF);
|
|
}
|