Andrea Di Biagio e54158504f [X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes. ... This patch teaches the DAGCombiner how to fold a binary OR between two shufflevector into a single shuffle vector when possible. The rules are: 1. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1) 2. fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2) The DAGCombiner can take advantage of the fact that OR is commutative and compute two possible shuffle masks (Mask1 and Mask2) for the resulting shuffle node. Before folding a dag according to either rule 1 or 2, DAGCombiner verifies that the resulting shuffle mask is legal for the target. DAGCombiner would firstly try to fold according to 1.; If not possible then it will try to fold according to 2. If both Mask1 and Mask2 are illegal then we conservatively don't fold the OR instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203156 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-06 20:19:52 +00:00
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AArch64	[AArch64] This is a work in progress to provide a machine description	2014-03-06 16:04:00 +00:00
ARM	ARM: Correctly align arguments after a byval struct is passed on the stack	2014-03-05 15:25:27 +00:00
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Mips	[Mips] Testcase typo fix. No functionality change.	2014-03-05 22:54:56 +00:00
MSP430
NVPTX
PowerPC	Fixup PPC Darwin i1 argument handling	2014-03-06 00:45:19 +00:00
R600	R600: Fix extloads from i8 / i16 to i64.	2014-03-06 17:34:12 +00:00
SPARC	[Sparc] Add support for parsing directives in SparcAsmParser.	2014-03-01 02:18:04 +00:00
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X86	[X86] Teach the DAGCombiner how to fold a OR of two shufflevector nodes.	2014-03-06 20:19:52 +00:00
XCore	[XCore] Add support for the "m" inline asm constraint.	2014-03-06 16:37:48 +00:00