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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171225 91177308-0d34-0410-b5e6-96231b3b80d8
166 lines
5.4 KiB
C++
166 lines
5.4 KiB
C++
//===-- HexagonAsmPrinter.h - Print machine code to an Hexagon .s file ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Hexagon Assembly printer class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef HEXAGONASMPRINTER_H
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#define HEXAGONASMPRINTER_H
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#include "Hexagon.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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class HexagonAsmPrinter : public AsmPrinter {
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const HexagonSubtarget *Subtarget;
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public:
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explicit HexagonAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer) {
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Subtarget = &TM.getSubtarget<HexagonSubtarget>();
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}
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virtual const char *getPassName() const {
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return "Hexagon Assembly Printer";
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}
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bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
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virtual void EmitInstruction(const MachineInstr *MI);
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virtual void EmitAlignment(unsigned NumBits,
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const GlobalValue *GV = 0) const;
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void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &OS);
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &OS);
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description. This method returns true if the
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/// machine instruction was sufficiently described to print it, otherwise it
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/// returns false.
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void printInstruction(const MachineInstr *MI, raw_ostream &O);
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// void printMachineInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO, raw_ostream &O);
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/// printRegister - Print register according to target requirements.
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///
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void printRegister(const MachineOperand &MO, bool R0AsZero,
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raw_ostream &O) {
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unsigned RegNo = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??");
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O << getRegisterName(RegNo);
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}
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void printImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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int value = MI->getOperand(OpNo).getImm();
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O << value;
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}
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void printNegImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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int value = MI->getOperand(OpNo).getImm();
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O << -value;
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}
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void printMEMriOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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const MachineOperand &MO1 = MI->getOperand(OpNo);
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const MachineOperand &MO2 = MI->getOperand(OpNo+1);
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O << getRegisterName(MO1.getReg())
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<< " + #"
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<< (int) MO2.getImm();
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}
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void printFrameIndexOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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const MachineOperand &MO1 = MI->getOperand(OpNo);
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const MachineOperand &MO2 = MI->getOperand(OpNo+1);
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O << getRegisterName(MO1.getReg())
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<< ", #"
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<< MO2.getImm();
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}
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void printBranchOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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// Branches can take an immediate operand. This is used by the branch
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// selection pass to print $+8, an eight byte displacement from the PC.
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if (MI->getOperand(OpNo).isImm()) {
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O << "$+" << MI->getOperand(OpNo).getImm()*4;
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} else {
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printOp(MI->getOperand(OpNo), O);
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}
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}
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void printCallOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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}
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void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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}
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void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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O << "#HI(";
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if (MI->getOperand(OpNo).isImm()) {
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printImmOperand(MI, OpNo, O);
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}
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else {
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printOp(MI->getOperand(OpNo), O);
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}
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O << ")";
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}
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void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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O << "#HI(";
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if (MI->getOperand(OpNo).isImm()) {
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printImmOperand(MI, OpNo, O);
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}
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else {
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printOp(MI->getOperand(OpNo), O);
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}
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O << ")";
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}
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void printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O);
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#if 0
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void printModuleLevelGV(const GlobalVariable* GVar, raw_ostream &O);
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#endif
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void printAddrModeBasePlusOffset(const MachineInstr *MI, int OpNo,
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raw_ostream &O);
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void printGlobalOperand(const MachineInstr *MI, int OpNo, raw_ostream &O);
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void printJumpTable(const MachineInstr *MI, int OpNo, raw_ostream &O);
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void printConstantPool(const MachineInstr *MI, int OpNo, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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#if 0
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void EmitStartOfAsmFile(Module &M);
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#endif
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};
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} // end of llvm namespace
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#endif
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