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e54885af9b
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in order to resolve the following issues with fmuladd (i.e. optional FMA) intrinsics: 1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd intrinsics even if the subtarget does not support FMA instructions, leading to laughably bad code generation in some situations. 2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128, resulting in a call to a software fp128 FMA implementation. 3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize, etc. to types that support hardware FMAs. The function has also been slightly renamed for consistency and to force a merge/build conflict for any out-of-tree target implementing it. To resolve, see comments and fixed in-tree examples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185956 91177308-0d34-0410-b5e6-96231b3b80d8
235 lines
9.9 KiB
C++
235 lines
9.9 KiB
C++
//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that SystemZ uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
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#define LLVM_TARGET_SystemZ_ISELLOWERING_H
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#include "SystemZ.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace SystemZISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Return with a flag operand. Operand 0 is the chain operand.
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RET_FLAG,
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// Calls a function. Operand 0 is the chain operand and operand 1
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// is the target address. The arguments start at operand 2.
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// There is an optional glue operand at the end.
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CALL,
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// Wraps a TargetGlobalAddress that should be loaded using PC-relative
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// accesses (LARL). Operand 0 is the address.
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PCREL_WRAPPER,
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// Signed integer and floating-point comparisons. The operands are the
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// two values to compare.
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CMP,
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// Likewise unsigned integer comparison.
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UCMP,
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// Branches if a condition is true. Operand 0 is the chain operand;
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// operand 1 is the 4-bit condition-code mask, with bit N in
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// big-endian order meaning "branch if CC=N"; operand 2 is the
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// target block and operand 3 is the flag operand.
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BR_CCMASK,
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// Selects between operand 0 and operand 1. Operand 2 is the
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// mask of condition-code values for which operand 0 should be
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// chosen over operand 1; it has the same form as BR_CCMASK.
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// Operand 3 is the flag operand.
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SELECT_CCMASK,
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// Evaluates to the gap between the stack pointer and the
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// base of the dynamically-allocatable area.
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ADJDYNALLOC,
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// Extracts the value of a 32-bit access register. Operand 0 is
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// the number of the register.
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EXTRACT_ACCESS,
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// Wrappers around the ISD opcodes of the same name. The output and
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// first input operands are GR128s. The trailing numbers are the
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// widths of the second operand in bits.
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UMUL_LOHI64,
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SDIVREM32,
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SDIVREM64,
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UDIVREM32,
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UDIVREM64,
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// Use MVC to copy bytes from one memory location to another.
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// The first operand is the target address, the second operand is the
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// source address, and the third operand is the constant length.
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// This isn't a memory opcode because we'd need to attach two
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// MachineMemOperands rather than one.
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MVC,
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// Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
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// ATOMIC_LOAD_<op>.
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//
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// Operand 0: the address of the containing 32-bit-aligned field
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// Operand 1: the second operand of <op>, in the high bits of an i32
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// for everything except ATOMIC_SWAPW
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// Operand 2: how many bits to rotate the i32 left to bring the first
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// operand into the high bits
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// Operand 3: the negative of operand 2, for rotating the other way
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// Operand 4: the width of the field in bits (8 or 16)
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ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
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ATOMIC_LOADW_ADD,
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ATOMIC_LOADW_SUB,
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ATOMIC_LOADW_AND,
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ATOMIC_LOADW_OR,
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ATOMIC_LOADW_XOR,
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ATOMIC_LOADW_NAND,
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ATOMIC_LOADW_MIN,
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ATOMIC_LOADW_MAX,
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ATOMIC_LOADW_UMIN,
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ATOMIC_LOADW_UMAX,
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// A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
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//
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// Operand 0: the address of the containing 32-bit-aligned field
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// Operand 1: the compare value, in the low bits of an i32
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// Operand 2: the swap value, in the low bits of an i32
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// Operand 3: how many bits to rotate the i32 left to bring the first
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// operand into the high bits
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// Operand 4: the negative of operand 2, for rotating the other way
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// Operand 5: the width of the field in bits (8 or 16)
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ATOMIC_CMP_SWAPW
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};
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}
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class SystemZSubtarget;
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class SystemZTargetMachine;
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class SystemZTargetLowering : public TargetLowering {
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public:
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explicit SystemZTargetLowering(SystemZTargetMachine &TM);
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// Override TargetLowering.
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virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
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return MVT::i32;
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}
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virtual EVT getSetCCResultType(LLVMContext &, EVT) const {
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return MVT::i32;
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}
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virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
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virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
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virtual std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT VT) const LLVM_OVERRIDE;
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virtual TargetLowering::ConstraintType
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getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
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virtual TargetLowering::ConstraintWeight
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getSingleConstraintMatchWeight(AsmOperandInfo &info,
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const char *constraint) const LLVM_OVERRIDE;
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virtual void
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LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const LLVM_OVERRIDE;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const LLVM_OVERRIDE;
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virtual SDValue LowerOperation(SDValue Op,
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SelectionDAG &DAG) const LLVM_OVERRIDE;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
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virtual SDValue
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LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
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virtual SDValue
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
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private:
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const SystemZSubtarget &Subtarget;
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const SystemZTargetMachine &TM;
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// Implement LowerOperation for individual opcodes.
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SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
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SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
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SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(BlockAddressSDNode *Node,
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SelectionDAG &DAG) const;
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SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
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SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
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unsigned Opcode) const;
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SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
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// If the last instruction before MBBI in MBB was some form of COMPARE,
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// try to replace it with a COMPARE AND BRANCH just before MBBI.
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// CCMask and Target are the BRC-like operands for the branch.
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// Return true if the change was made.
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bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned CCMask,
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MachineBasicBlock *Target) const;
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// Implement EmitInstrWithCustomInserter for individual operation types.
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MachineBasicBlock *emitSelect(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitCondStore(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned StoreOpcode, bool Invert) const;
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MachineBasicBlock *emitExt128(MachineInstr *MI,
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MachineBasicBlock *MBB,
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bool ClearEven, unsigned SubReg) const;
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MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned BinOpcode, unsigned BitSize,
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bool Invert = false) const;
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MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
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MachineBasicBlock *MBB,
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unsigned CompareOpcode,
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unsigned KeepOldMask,
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unsigned BitSize) const;
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MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitMVCWrapper(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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};
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} // end namespace llvm
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#endif // LLVM_TARGET_SystemZ_ISELLOWERING_H
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