mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-08 19:06:39 +00:00
e560d526a1
Tested-by: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188515 91177308-0d34-0410-b5e6-96231b3b80d8
265 lines
8.1 KiB
LLVM
265 lines
8.1 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
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;===------------------------------------------------------------------------===;
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; GLOBAL ADDRESS SPACE
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;===------------------------------------------------------------------------===;
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; Load an i8 value from the global address space.
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; R600-CHECK: @load_i8
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; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_i8
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; SI-CHECK: BUFFER_LOAD_UBYTE VGPR{{[0-9]+}},
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define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%1 = load i8 addrspace(1)* %in
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%2 = zext i8 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @load_i8_sext
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; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600-CHECK: 24
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600-CHECK: 24
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; SI-CHECK: @load_i8_sext
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; SI-CHECK: BUFFER_LOAD_SBYTE
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define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
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entry:
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%0 = load i8 addrspace(1)* %in
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%1 = sext i8 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Load an i16 value from the global address space.
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; R600-CHECK: @load_i16
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; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_i16
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; SI-CHECK: BUFFER_LOAD_USHORT
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define void @load_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
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entry:
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%0 = load i16 addrspace(1)* %in
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%1 = zext i16 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @load_i16_sext
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; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600-CHECK: 16
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600-CHECK: 16
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; SI-CHECK: @load_i16_sext
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; SI-CHECK: BUFFER_LOAD_SSHORT
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define void @load_i16_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
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entry:
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%0 = load i16 addrspace(1)* %in
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%1 = sext i16 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; load an i32 value from the global address space.
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; R600-CHECK: @load_i32
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_i32
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; SI-CHECK: BUFFER_LOAD_DWORD VGPR{{[0-9]+}}
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define void @load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = load i32 addrspace(1)* %in
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; load a f32 value from the global address space.
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; R600-CHECK: @load_f32
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_f32
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; SI-CHECK: BUFFER_LOAD_DWORD VGPR{{[0-9]+}}
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define void @load_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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entry:
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%0 = load float addrspace(1)* %in
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store float %0, float addrspace(1)* %out
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ret void
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}
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; load a v2f32 value from the global address space
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; R600-CHECK: @load_v2f32
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; R600-CHECK: VTX_READ_64
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; SI-CHECK: @load_v2f32
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; SI-CHECK: BUFFER_LOAD_DWORDX2
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define void @load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
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entry:
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%0 = load <2 x float> addrspace(1)* %in
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @load_i64
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; R600-CHECK: MEM_RAT
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; R600-CHECK: MEM_RAT
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; SI-CHECK: @load_i64
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; SI-CHECK: BUFFER_LOAD_DWORDX2
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define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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entry:
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%0 = load i64 addrspace(1)* %in
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store i64 %0, i64 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @load_i64_sext
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; R600-CHECK: MEM_RAT
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; R600-CHECK: MEM_RAT
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.x
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; R600-CHECK: 31
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; SI-CHECK: @load_i64_sext
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; SI-CHECK: BUFFER_LOAD_DWORDX2 [[VAL:VGPR[0-9]_VGPR[0-9]]]
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; SI-CHECK: V_LSHL_B64 [[LSHL:VGPR[0-9]_VGPR[0-9]]], [[VAL]], 32
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; SI-CHECK: V_ASHR_I64 VGPR{{[0-9]}}_VGPR{{[0-9]}}, [[LSHL]], 32
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define void @load_i64_sext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = load i32 addrspace(1)* %in
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%1 = sext i32 %0 to i64
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @load_i64_zext
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; R600-CHECK: MEM_RAT
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; R600-CHECK: MEM_RAT
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define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = load i32 addrspace(1)* %in
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%1 = zext i32 %0 to i64
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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;===------------------------------------------------------------------------===;
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; CONSTANT ADDRESS SPACE
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;===------------------------------------------------------------------------===;
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; Load a sign-extended i8 value
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; R600-CHECK: @load_const_i8_sext
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; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600-CHECK: 24
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600-CHECK: 24
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; SI-CHECK: @load_const_i8_sext
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; SI-CHECK: BUFFER_LOAD_SBYTE VGPR{{[0-9]+}},
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define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
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entry:
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%0 = load i8 addrspace(2)* %in
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%1 = sext i8 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Load an aligned i8 value
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; R600-CHECK: @load_const_i8_aligned
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; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_const_i8_aligned
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; SI-CHECK: BUFFER_LOAD_UBYTE VGPR{{[0-9]+}},
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define void @load_const_i8_aligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
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entry:
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%0 = load i8 addrspace(2)* %in
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%1 = zext i8 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Load an un-aligned i8 value
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; R600-CHECK: @load_const_i8_unaligned
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; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_const_i8_unaligned
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; SI-CHECK: BUFFER_LOAD_UBYTE VGPR{{[0-9]+}},
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define void @load_const_i8_unaligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
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entry:
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%0 = getelementptr i8 addrspace(2)* %in, i32 1
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%1 = load i8 addrspace(2)* %0
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%2 = zext i8 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; Load a sign-extended i16 value
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; R600-CHECK: @load_const_i16_sext
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; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600-CHECK: 16
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600-CHECK: 16
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; SI-CHECK: @load_const_i16_sext
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; SI-CHECK: BUFFER_LOAD_SSHORT
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define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
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entry:
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%0 = load i16 addrspace(2)* %in
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%1 = sext i16 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Load an aligned i16 value
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; R600-CHECK: @load_const_i16_aligned
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; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_const_i16_aligned
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; SI-CHECK: BUFFER_LOAD_USHORT
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define void @load_const_i16_aligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
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entry:
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%0 = load i16 addrspace(2)* %in
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%1 = zext i16 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Load an un-aligned i16 value
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; R600-CHECK: @load_const_i16_unaligned
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; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_const_i16_unaligned
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; SI-CHECK: BUFFER_LOAD_USHORT
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define void @load_const_i16_unaligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
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entry:
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%0 = getelementptr i16 addrspace(2)* %in, i32 1
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%1 = load i16 addrspace(2)* %0
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%2 = zext i16 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; Load an i32 value from the constant address space.
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; R600-CHECK: @load_const_addrspace_i32
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_const_addrspace_i32
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; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]+}}
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define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) {
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entry:
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%0 = load i32 addrspace(2)* %in
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; Load a f32 value from the constant address space.
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; R600-CHECK: @load_const_addrspace_f32
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_const_addrspace_f32
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; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]+}}
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define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) {
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%1 = load float addrspace(2)* %in
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store float %1, float addrspace(1)* %out
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ret void
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}
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