Weiming Zhao e56764bad1 Remove hard coded registers in ARM ldrexd and strexd instructions ... This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8		2012-11-16 21:55:34 +00:00
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ARM	Remove hard coded registers in ARM ldrexd and strexd instructions	2012-11-16 21:55:34 +00:00
CPP
Generic	Codegen support for arbitrary vector getelementptrs.	2012-11-13 13:01:58 +00:00
Hexagon	test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the failure on i686 hosts.	2012-11-14 22:22:37 +00:00
MBlaze
Mips	[mips] Fix delay slot filler so that instructions with register operand $1 are	2012-11-16 02:39:34 +00:00
MSP430
NVPTX	[NVPTX] Order global variables in def-use order before emiting them in the final assembly	2012-11-16 21:03:51 +00:00
PowerPC	PowerPC: Lowering floor intrinsic for Altivec	2012-11-15 20:56:03 +00:00
SPARC	Use TargetTransformInfo to control switch-to-lookup table transformation	2012-10-30 11:23:25 +00:00
Thumb	Convert an improper CodeGen test to a MC test.	2012-11-10 04:30:40 +00:00
Thumb2	Add GPRPair Register class to ARM.	2012-10-26 21:29:15 +00:00
X86	llvm/test/CodeGen/X86/hipe-cc*.ll: Add explicit -mcpu, or they don't expect to pass on Atom.	2012-11-16 16:07:37 +00:00
XCore	Fix handling of aliases to functions.	2012-11-16 21:12:38 +00:00