llvm-6502/test/CodeGen
Evan Cheng e573fb3255 More fcopysign correctness and performance fix.
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.

The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
        vmov.i32        d1, #0x80000000
        vbsl    d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126295 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 02:24:55 +00:00
..
Alpha
ARM More fcopysign correctness and performance fix. 2011-02-23 02:24:55 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips
MSP430
PowerPC
PTX
SPARC
SystemZ
Thumb
Thumb2
X86 Revert r126195, "test/CodeGen/X86/vec_cast.ll: Mark as XFAIL: migw,win32 for workaround of PR8311." 2011-02-22 08:22:54 +00:00
XCore