llvm-6502/include/llvm/Target
2009-10-15 18:49:26 +00:00
..
SubtargetFeature.h Switch SubtargetFeature off of ostreams 2009-08-23 21:41:43 +00:00
Target.td Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When 2009-10-01 08:21:18 +00:00
TargetAsmParser.h Added the ParseInstruction() hook for target specific assembler directives so 2009-09-10 20:51:44 +00:00
TargetCallingConv.td
TargetData.h Try again at privatizing the layout info map, with a rewritten patch. 2009-08-21 19:59:12 +00:00
TargetELFWriterInfo.h
TargetFrameInfo.h Use explicit structs instead of std::pair to map callee saved regs to spill slots. 2009-09-27 17:58:47 +00:00
TargetInstrDesc.h Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When 2009-10-01 08:21:18 +00:00
TargetInstrInfo.h Revert the kludge in 76703. I got a clean 2009-10-12 18:49:00 +00:00
TargetInstrItineraries.h Make the end-of-itinerary mark explicit. Some cleanup. 2009-09-24 20:22:50 +00:00
TargetIntrinsicInfo.h Clean up TargetIntrinsicInfo API. Add pure virtual methods. 2009-10-15 18:49:26 +00:00
TargetJITInfo.h
TargetLowering.h Update comments. 2009-09-19 10:08:51 +00:00
TargetLoweringObjectFile.h Use OutStreamer.SwitchSection instead of writing out textual section directives. 2009-09-30 22:25:37 +00:00
TargetMachine.h Add a target hook to add pre- post-regalloc scheduling passes. 2009-09-30 08:49:50 +00:00
TargetMachOWriterInfo.h
TargetOptions.h Implement the JIT side of the GDB JIT debugging interface. To enable this 2009-09-20 23:52:43 +00:00
TargetRegisterInfo.h Add a const qualifier. 2009-10-09 22:09:05 +00:00
TargetRegistry.h remove a dead method. 2009-09-20 22:46:42 +00:00
TargetSchedule.td Fix apostrophos. 2009-09-15 15:08:33 +00:00
TargetSelect.h
TargetSelectionDAG.td
TargetSubtarget.h Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. 2009-09-30 00:10:16 +00:00