mirror of
https://github.com/c64scene-ar/llvm-6502.git
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5ffe917f72
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80975 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.7 KiB
LLVM
77 lines
2.7 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
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;CHECK: vcvt_f32tos32:
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;CHECK: vcvt.s32.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
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ret <2 x i32> %tmp2
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}
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define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
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;CHECK: vcvt_f32tou32:
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;CHECK: vcvt.u32.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
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;CHECK: vcvt_s32tof32:
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;CHECK: vcvt.f32.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
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ret <2 x float> %tmp2
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}
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define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
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;CHECK: vcvt_u32tof32:
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;CHECK: vcvt.f32.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
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ret <2 x float> %tmp2
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}
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declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
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;CHECK: vcvtQ_f32tos32:
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;CHECK: vcvt.s32.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
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ret <4 x i32> %tmp2
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}
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define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
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;CHECK: vcvtQ_f32tou32:
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;CHECK: vcvt.u32.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
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;CHECK: vcvtQ_s32tof32:
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;CHECK: vcvt.f32.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
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ret <4 x float> %tmp2
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}
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define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
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;CHECK: vcvtQ_u32tof32:
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;CHECK: vcvt.f32.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
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ret <4 x float> %tmp2
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}
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declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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