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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
268 lines
8.5 KiB
C++
268 lines
8.5 KiB
C++
//===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements hazard recognizers for scheduling on PowerPC processors.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#include "PPCHazardRecognizers.h"
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#include "PPC.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// PowerPC 970 Hazard Recognizer
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//
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// This models the dispatch group formation of the PPC970 processor. Dispatch
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// groups are bundles of up to five instructions that can contain up to two ALU
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// (aka FXU) ops, two FPU ops, two Load/Store ops, one CR op, one VALU op, one
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// VPERM op, and one BRANCH op. If the code contains more instructions in a
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// sequence than the dispatch group can contain (e.g. three loads in a row) the
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// processor terminates the dispatch group early, wasting execution resources.
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//
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// In addition to these restrictions, there are a number of other restrictions:
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// some instructions, e.g. branches, are required to be the last instruction in
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// a group. Additionally, only branches can issue in the 5th (last) slot.
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//
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// Finally, there are a number of "structural" hazards on the PPC970. These
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// conditions cause large performance penalties due to misprediction, recovery,
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// and replay logic that has to happen. These cases include setting a CTR and
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// branching through it in the same dispatch group, and storing to an address,
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// then loading from the same address within a dispatch group. To avoid these
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// conditions, we insert no-op instructions when appropriate.
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//
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// FIXME: This is missing some significant cases:
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// -1. Handle all of the instruction types in GetInstrType.
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// 0. Handling of instructions that must be the first/last in a group.
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// 1. Modeling of microcoded instructions.
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// 2. Handling of cracked instructions.
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// 3. Handling of serialized operations.
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// 4. Handling of the esoteric cases in "Resource-based Instruction Grouping",
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// e.g. integer divides that only execute in the second slot.
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//
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PPCHazardRecognizer970::PPCHazardRecognizer970() {
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EndDispatchGroup();
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}
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void PPCHazardRecognizer970::EndDispatchGroup() {
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DEBUG(std::cerr << "=== Start of dispatch group\n");
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// Pipeline units.
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NumFXU = NumLSU = NumFPU = 0;
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HasCR = HasSPR = HasVALU = HasVPERM = false;
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NumIssued = 0;
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// Structural hazard info.
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HasCTRSet = false;
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StorePtr1 = StorePtr2 = SDOperand();
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StoreSize = 0;
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}
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PPCHazardRecognizer970::PPC970InstrType
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PPCHazardRecognizer970::GetInstrType(unsigned Opcode) {
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if (Opcode < ISD::BUILTIN_OP_END)
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return PseudoInst;
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Opcode -= ISD::BUILTIN_OP_END;
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switch (Opcode) {
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case PPC::FMRSD: return PseudoInst; // Usually coallesced away.
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case PPC::BCTRL:
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case PPC::BL:
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case PPC::BLA:
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return BR;
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case PPC::MCRF:
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case PPC::MFCR:
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case PPC::MFOCRF:
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return CR;
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case PPC::MFLR:
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case PPC::MFCTR:
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case PPC::MTLR:
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case PPC::MTCTR:
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return SPR;
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case PPC::LFS:
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case PPC::LFD:
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case PPC::LWZ:
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case PPC::LFSX:
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case PPC::LWZX:
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case PPC::LBZ:
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case PPC::LHA:
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case PPC::LHZ:
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case PPC::LWZU:
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return LSU_LD;
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case PPC::STFS:
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case PPC::STFD:
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case PPC::STW:
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case PPC::STB:
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case PPC::STH:
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case PPC::STWU:
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return LSU_ST;
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case PPC::DIVW:
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case PPC::DIVWU:
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case PPC::DIVD:
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case PPC::DIVDU:
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return FXU_FIRST;
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case PPC::FADDS:
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case PPC::FCTIWZ:
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case PPC::FRSP:
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case PPC::FSUB:
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return FPU;
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}
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return FXU;
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}
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/// isLoadOfStoredAddress - If we have a load from the previously stored pointer
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/// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
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bool PPCHazardRecognizer970::
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isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const {
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// Handle exact and commuted addresses.
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if (Ptr1 == StorePtr1 && Ptr2 == StorePtr2)
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return true;
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if (Ptr2 == StorePtr1 && Ptr1 == StorePtr2)
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return true;
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// Okay, we don't have an exact match, if this is an indexed offset, see if we
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// have overlap (which happens during fp->int conversion for example).
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if (StorePtr2 == Ptr2) {
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if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1))
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if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
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// Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check to
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// see if the load and store actually overlap.
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int StoreOffs = StoreOffset->getValue();
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int LoadOffs = LoadOffset->getValue();
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if (StoreOffs < LoadOffs) {
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if (int(StoreOffs+StoreSize) > LoadOffs) return true;
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} else {
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if (int(LoadOffs+LoadSize) > StoreOffs) return true;
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}
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}
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}
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return false;
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}
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/// getHazardType - We return hazard for any non-branch instruction that would
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/// terminate terminate the dispatch group. We turn NoopHazard for any
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/// instructions that wouldn't terminate the dispatch group that would cause a
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/// pipeline flush.
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HazardRecognizer::HazardType PPCHazardRecognizer970::
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getHazardType(SDNode *Node) {
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PPC970InstrType InstrType = GetInstrType(Node->getOpcode());
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if (InstrType == PseudoInst) return NoHazard;
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unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
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switch (InstrType) {
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default: assert(0 && "Unknown instruction type!");
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case FXU:
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case FXU_FIRST: if (NumFXU == 2) return Hazard;
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case LSU_ST:
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case LSU_LD: if (NumLSU == 2) return Hazard;
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case FPU: if (NumFPU == 2) return Hazard;
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case CR: if (HasCR) return Hazard;
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case SPR: if (HasSPR) return Hazard;
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case VALU: if (HasVALU) return Hazard;
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case VPERM: if (HasVPERM) return Hazard;
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case BR: break;
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}
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// We can only issue a CR or SPR instruction, or an FXU instruction that needs
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// to lead a dispatch group as the first instruction in the group.
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if (NumIssued != 0 &&
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(InstrType == CR || InstrType == SPR || InstrType == FXU_FIRST))
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return Hazard;
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// We can only issue a branch as the last instruction in a group.
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if (NumIssued == 4 && InstrType != BR)
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return Hazard;
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// Do not allow MTCTR and BCTRL to be in the same dispatch group.
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if (HasCTRSet && Opcode == PPC::BCTRL)
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return NoopHazard;
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// If this is a load following a store, make sure it's not to the same or
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// overlapping address.
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if (InstrType == LSU_LD && StoreSize) {
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unsigned LoadSize;
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switch (Opcode) {
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default: assert(0 && "Unknown load!");
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case PPC::LBZ: LoadSize = 1; break;
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case PPC::LHA:
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case PPC::LHZ: LoadSize = 2; break;
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case PPC::LWZU:
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case PPC::LFSX:
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case PPC::LFS:
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case PPC::LWZX:
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case PPC::LWZ: LoadSize = 4; break;
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case PPC::LFD: LoadSize = 8; break;
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}
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if (isLoadOfStoredAddress(LoadSize,
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Node->getOperand(0), Node->getOperand(1)))
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return NoopHazard;
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}
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return NoHazard;
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}
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void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
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PPC970InstrType InstrType = GetInstrType(Node->getOpcode());
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if (InstrType == PseudoInst) return;
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unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
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// Update structural hazard information.
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if (Opcode == PPC::MTCTR) HasCTRSet = true;
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// Track the address stored to.
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if (InstrType == LSU_ST) {
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StorePtr1 = Node->getOperand(1);
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StorePtr2 = Node->getOperand(2);
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switch (Opcode) {
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default: assert(0 && "Unknown store instruction!");
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case PPC::STB: StoreSize = 1; break;
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case PPC::STH: StoreSize = 2; break;
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case PPC::STFS:
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case PPC::STWU:
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case PPC::STW: StoreSize = 4; break;
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case PPC::STFD: StoreSize = 8; break;
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}
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}
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switch (InstrType) {
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default: assert(0 && "Unknown instruction type!");
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case FXU:
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case FXU_FIRST: ++NumFXU; break;
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case LSU_LD:
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case LSU_ST: ++NumLSU; break;
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case FPU: ++NumFPU; break;
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case CR: HasCR = true; break;
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case SPR: HasSPR = true; break;
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case VALU: HasVALU = true; break;
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case VPERM: HasVPERM = true; break;
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case BR: NumIssued = 4; return; // ends a d-group.
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}
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++NumIssued;
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if (NumIssued == 5)
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EndDispatchGroup();
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}
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void PPCHazardRecognizer970::AdvanceCycle() {
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assert(NumIssued < 5 && "Illegal dispatch group!");
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++NumIssued;
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if (NumIssued == 5)
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EndDispatchGroup();
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}
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void PPCHazardRecognizer970::EmitNoop() {
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AdvanceCycle();
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}
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