mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 20:29:21 +00:00
86050dc8cc
- This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
2.5 KiB
LLVM
95 lines
2.5 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
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define void @foo(i32 %X, i32 %Y) {
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entry:
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; CHECK: foo:
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; CHECK: it ne
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; CHECK: cmpne
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; CHECK: it hi
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; CHECK: pophi {r7, pc}
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%tmp1 = icmp ult i32 %X, 4 ; <i1> [#uses=1]
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%tmp4 = icmp eq i32 %Y, 0 ; <i1> [#uses=1]
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%tmp7 = or i1 %tmp4, %tmp1 ; <i1> [#uses=1]
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br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock
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cond_true: ; preds = %entry
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%tmp10 = call i32 (...)* @bar( ) ; <i32> [#uses=0]
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ret void
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UnifiedReturnBlock: ; preds = %entry
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ret void
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}
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declare i32 @bar(...)
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; FIXME: Need post-ifcvt branch folding to get rid of the extra br at end of BB1.
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%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
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define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
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entry:
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; CHECK: CountTree:
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; CHECK: it eq
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; CHECK: cmpeq
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; CHECK: bne
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; CHECK: cmp
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; CHECK: itt eq
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; CHECK: moveq
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; CHECK: popeq
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br label %tailrecurse
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tailrecurse: ; preds = %bb, %entry
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%tmp6 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
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%tmp9 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=2]
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%tmp12 = load %struct.quad_struct** null ; <%struct.quad_struct*> [#uses=1]
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%tmp14 = icmp eq %struct.quad_struct* null, null ; <i1> [#uses=1]
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%tmp17 = icmp eq %struct.quad_struct* %tmp6, null ; <i1> [#uses=1]
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%tmp23 = icmp eq %struct.quad_struct* %tmp9, null ; <i1> [#uses=1]
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%tmp29 = icmp eq %struct.quad_struct* %tmp12, null ; <i1> [#uses=1]
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%bothcond = and i1 %tmp17, %tmp14 ; <i1> [#uses=1]
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%bothcond1 = and i1 %bothcond, %tmp23 ; <i1> [#uses=1]
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%bothcond2 = and i1 %bothcond1, %tmp29 ; <i1> [#uses=1]
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br i1 %bothcond2, label %return, label %bb
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bb: ; preds = %tailrecurse
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%tmp41 = tail call fastcc i32 @CountTree( %struct.quad_struct* %tmp9 ) ; <i32> [#uses=0]
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br label %tailrecurse
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return: ; preds = %tailrecurse
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ret i32 0
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}
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%struct.SString = type { i8*, i32, i32 }
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declare void @abort()
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define fastcc void @t1(%struct.SString* %word, i8 signext %c) {
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entry:
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; CHECK: t1:
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; CHECK: it ne
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; CHECK: popne {r7, pc}
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%tmp1 = icmp eq %struct.SString* %word, null ; <i1> [#uses=1]
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br i1 %tmp1, label %cond_true, label %cond_false
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cond_true: ; preds = %entry
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tail call void @abort( )
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unreachable
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cond_false: ; preds = %entry
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ret void
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}
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define fastcc void @t2() nounwind {
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entry:
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; CHECK: t2:
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; CHECK: cmp r0, #0
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; CHECK: beq
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br i1 undef, label %bb.i.i3, label %growMapping.exit
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bb.i.i3: ; preds = %entry
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unreachable
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growMapping.exit: ; preds = %entry
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unreachable
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}
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