mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-16 11:05:54 +00:00
85cc972a06
using two instructions (sethi and store). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183090 91177308-0d34-0410-b5e6-96231b3b80d8
280 lines
5.6 KiB
LLVM
280 lines
5.6 KiB
LLVM
; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
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; RUN: llc < %s -march=sparcv9 | FileCheck %s -check-prefix=OPT
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; CHECK: ret2:
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; CHECK: or %g0, %i1, %i0
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; OPT: ret2:
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; OPT: jmp %o7+8
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; OPT: or %g0, %o1, %o0
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define i64 @ret2(i64 %a, i64 %b) {
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ret i64 %b
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}
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; CHECK: shl_imm
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; CHECK: sllx %i0, 7, %i0
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; OPT: shl_imm:
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; OPT: jmp %o7+8
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; OPT: sllx %o0, 7, %o0
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define i64 @shl_imm(i64 %a) {
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%x = shl i64 %a, 7
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ret i64 %x
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}
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; CHECK: sra_reg
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; CHECK: srax %i0, %i1, %i0
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; OPT: sra_reg:
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; OPT: jmp %o7+8
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; OPT: srax %o0, %o1, %o0
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define i64 @sra_reg(i64 %a, i64 %b) {
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%x = ashr i64 %a, %b
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ret i64 %x
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}
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; Immediate materialization. Many of these patterns could actually be merged
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; into the restore instruction:
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;
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; restore %g0, %g0, %o0
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;
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; CHECK: ret_imm0
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; CHECK: or %g0, 0, %i0
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; OPT: ret_imm0
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; OPT: jmp %o7+8
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; OPT: or %g0, 0, %o0
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define i64 @ret_imm0() {
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ret i64 0
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}
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; CHECK: ret_simm13
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; CHECK: or %g0, -4096, %i0
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; OPT: ret_simm13
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; OPT: jmp %o7+8
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; OPT: or %g0, -4096, %o0
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define i64 @ret_simm13() {
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ret i64 -4096
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}
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; CHECK: ret_sethi
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; CHECK: sethi 4, %i0
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; CHECK-NOT: or
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; CHECK: restore
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; OPT: ret_sethi
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; OPT: jmp %o7+8
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; OPT: sethi 4, %o0
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define i64 @ret_sethi() {
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ret i64 4096
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}
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; CHECK: ret_sethi_or
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; CHECK: sethi 4, [[R:%[goli][0-7]]]
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; CHECK: or [[R]], 1, %i0
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; OPT: ret_sethi_or
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; OPT: sethi 4, [[R:%[go][0-7]]]
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; OPT: jmp %o7+8
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; OPT: or [[R]], 1, %o0
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define i64 @ret_sethi_or() {
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ret i64 4097
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}
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; CHECK: ret_nimm33
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; CHECK: sethi 4, [[R:%[goli][0-7]]]
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; CHECK: xor [[R]], -4, %i0
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; OPT: ret_nimm33
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; OPT: sethi 4, [[R:%[go][0-7]]]
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; OPT: jmp %o7+8
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; OPT: xor [[R]], -4, %o0
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define i64 @ret_nimm33() {
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ret i64 -4100
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}
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; CHECK: ret_bigimm
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; CHECK: sethi
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; CHECK: sethi
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define i64 @ret_bigimm() {
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ret i64 6800754272627607872
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}
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; CHECK: ret_bigimm2
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; CHECK: sethi 1048576
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define i64 @ret_bigimm2() {
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ret i64 4611686018427387904 ; 0x4000000000000000
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}
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; CHECK: reg_reg_alu
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; CHECK: add %i0, %i1, [[R0:%[goli][0-7]]]
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; CHECK: sub [[R0]], %i2, [[R1:%[goli][0-7]]]
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; CHECK: andn [[R1]], %i0, %i0
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define i64 @reg_reg_alu(i64 %x, i64 %y, i64 %z) {
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%a = add i64 %x, %y
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%b = sub i64 %a, %z
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%c = xor i64 %x, -1
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%d = and i64 %b, %c
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ret i64 %d
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}
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; CHECK: reg_imm_alu
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; CHECK: add %i0, -5, [[R0:%[goli][0-7]]]
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; CHECK: xor [[R0]], 2, %i0
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define i64 @reg_imm_alu(i64 %x, i64 %y, i64 %z) {
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%a = add i64 %x, -5
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%b = xor i64 %a, 2
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ret i64 %b
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}
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; CHECK: loads
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; CHECK: ldx [%i0]
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; CHECK: stx %
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; CHECK: ld [%i1]
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; CHECK: st %
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; CHECK: ldsw [%i2]
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; CHECK: stx %
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; CHECK: ldsh [%i3]
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; CHECK: sth %
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define i64 @loads(i64* %p, i32* %q, i32* %r, i16* %s) {
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%a = load i64* %p
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%ai = add i64 1, %a
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store i64 %ai, i64* %p
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%b = load i32* %q
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%b2 = zext i32 %b to i64
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%bi = trunc i64 %ai to i32
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store i32 %bi, i32* %q
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%c = load i32* %r
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%c2 = sext i32 %c to i64
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store i64 %ai, i64* %p
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%d = load i16* %s
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%d2 = sext i16 %d to i64
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%di = trunc i64 %ai to i16
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store i16 %di, i16* %s
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%x1 = add i64 %a, %b2
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%x2 = add i64 %c2, %d2
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%x3 = add i64 %x1, %x2
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ret i64 %x3
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}
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; CHECK: stores
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; CHECK: ldx [%i0+8], [[R:%[goli][0-7]]]
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; CHECK: stx [[R]], [%i0+16]
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; CHECK: st [[R]], [%i1+-8]
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; CHECK: sth [[R]], [%i2+40]
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; CHECK: stb [[R]], [%i3+-20]
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define void @stores(i64* %p, i32* %q, i16* %r, i8* %s) {
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%p1 = getelementptr i64* %p, i64 1
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%p2 = getelementptr i64* %p, i64 2
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%pv = load i64* %p1
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store i64 %pv, i64* %p2
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%q2 = getelementptr i32* %q, i32 -2
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%qv = trunc i64 %pv to i32
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store i32 %qv, i32* %q2
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%r2 = getelementptr i16* %r, i16 20
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%rv = trunc i64 %pv to i16
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store i16 %rv, i16* %r2
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%s2 = getelementptr i8* %s, i8 -20
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%sv = trunc i64 %pv to i8
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store i8 %sv, i8* %s2
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ret void
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}
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; CHECK: promote_shifts
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; CHECK: ldub [%i0], [[R:%[goli][0-7]]]
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; CHECK: sll [[R]], [[R]], %i0
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define i8 @promote_shifts(i8* %p) {
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%L24 = load i8* %p
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%L32 = load i8* %p
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%B36 = shl i8 %L24, %L32
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ret i8 %B36
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}
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; CHECK: multiply
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; CHECK: mulx %i0, %i1, %i0
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define i64 @multiply(i64 %a, i64 %b) {
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%r = mul i64 %a, %b
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ret i64 %r
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}
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; CHECK: signed_divide
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; CHECK: sdivx %i0, %i1, %i0
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define i64 @signed_divide(i64 %a, i64 %b) {
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%r = sdiv i64 %a, %b
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ret i64 %r
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}
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; CHECK: unsigned_divide
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; CHECK: udivx %i0, %i1, %i0
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define i64 @unsigned_divide(i64 %a, i64 %b) {
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%r = udiv i64 %a, %b
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ret i64 %r
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}
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define void @access_fi() {
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entry:
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%b = alloca [32 x i8], align 1
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%arraydecay = getelementptr inbounds [32 x i8]* %b, i64 0, i64 0
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call void @g(i8* %arraydecay) #2
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ret void
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}
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declare void @g(i8*)
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; CHECK: expand_setcc
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; CHECK: subcc %i0, 1,
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; CHECK: movl %xcc, 1,
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define i32 @expand_setcc(i64 %a) {
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%cond = icmp sle i64 %a, 0
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%cast2 = zext i1 %cond to i32
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%RV = sub i32 1, %cast2
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ret i32 %RV
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}
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; CHECK: spill_i64
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; CHECK: stx
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; CHECK: ldx
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define i64 @spill_i64(i64 %x) {
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call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7}"()
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ret i64 %x
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}
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; CHECK: bitcast_i64_f64
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; CHECK: std
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; CHECK: ldx
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define i64 @bitcast_i64_f64(double %x) {
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%y = bitcast double %x to i64
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ret i64 %y
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}
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; CHECK: bitcast_f64_i64
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; CHECK: stx
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; CHECK: ldd
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define double @bitcast_f64_i64(i64 %x) {
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%y = bitcast i64 %x to double
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ret double %y
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}
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; CHECK: store_zero:
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; CHECK: stx %g0, [%i0]
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; CHECK: stx %g0, [%i1+8]
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; OPT: store_zero:
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; OPT: stx %g0, [%o0]
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; OPT: stx %g0, [%o1+8]
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define i64 @store_zero(i64* nocapture %a, i64* nocapture %b) {
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entry:
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store i64 0, i64* %a, align 8
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%0 = getelementptr inbounds i64* %b, i32 1
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store i64 0, i64* %0, align 8
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ret i64 0
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}
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