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9d760ae5c6
nonvolatile condition register fields across calls under the SVR4 ABIs.
* With the 64-bit ABI, the save location is at a fixed offset of 8 from
the stack pointer. The frame pointer cannot be used to access this
portion of the stack frame since the distance from the frame pointer may
change with alloca calls.
* With the 32-bit ABI, the save location is just below the general
register save area, and is accessed via the frame pointer like the rest
of the save areas. This is an optional slot, so it must only be created
if any of CR2, CR3, and CR4 were modified.
* For both ABIs, save/restore logic is generated only if one of the
nonvolatile CR fields were modified.
I also took this opportunity to clean up an extra FIXME in
PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless
for the 64-bit ABI, so I removed them for correctness and efficiency.
Fixes PR13708 and partially also PR13623. It lets us enable exception handling
on PPC64.
Patch by William J. Schmidt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163713 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.4 KiB
LLVM
50 lines
1.4 KiB
LLVM
; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32
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; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64
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declare void @foo()
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define i32 @test_cr2() nounwind {
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entry:
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%ret = alloca i32, align 4
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%0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
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store i32 %0, i32* %ret, align 4
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call void @foo()
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%1 = load i32* %ret, align 4
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ret i32 %1
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}
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; PPC32: mfcr 12
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; PPC32-NEXT: stw 12, {{[0-9]+}}(31)
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; PPC32: lwz 12, {{[0-9]+}}(31)
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; PPC32-NEXT: mtcrf 32, 12
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; PPC64: mfcr 12
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; PPC64-NEXT: stw 12, 8(1)
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; PPC64: lwz 12, 8(1)
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; PPC64-NEXT: mtcrf 32, 12
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define i32 @test_cr234() nounwind {
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entry:
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%ret = alloca i32, align 4
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%0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09cmp 3,$2,$2\0A\09cmp 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind
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store i32 %0, i32* %ret, align 4
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call void @foo()
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%1 = load i32* %ret, align 4
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ret i32 %1
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}
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; PPC32: mfcr 12
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; PPC32-NEXT: stw 12, {{[0-9]+}}(31)
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; PPC32: lwz 12, {{[0-9]+}}(31)
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; PPC32-NEXT: mtcrf 32, 12
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; PPC32-NEXT: mtcrf 16, 12
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; PPC32-NEXT: mtcrf 8, 12
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; PPC64: mfcr 12
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; PPC64-NEXT: stw 12, 8(1)
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; PPC64: lwz 12, 8(1)
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; PPC64-NEXT: mtcrf 32, 12
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; PPC64-NEXT: mtcrf 16, 12
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; PPC64-NEXT: mtcrf 8, 12
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